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https://github.com/RTimothyEdwards/magic.git
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R. Timothy Edwards
b4912fd550
version 8.3.521 that, due to an argument size mismatch, causes device parameters in netlist output to be printed as zero. Also added a small extension to the list of extraction types to include "device veriloga", which has the same syntax as "device subcircuit" but generates a component type "N" (Verilog-A component) in the netlist output.
152 lines
5.2 KiB
C
152 lines
5.2 KiB
C
/*
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* extract.h --
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*
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* Defines the exported interface to the circuit extractor.
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*
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* rcsid "$Header: /usr/cvsroot/magic-8.0/extract/extract.h,v 1.3 2009/01/30 03:51:02 tim Exp $"
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*
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* *********************************************************************
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* * Copyright (C) 1985, 1990 Regents of the University of California. *
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* * Permission to use, copy, modify, and distribute this *
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* * software and its documentation for any purpose and without *
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* * fee is hereby granted, provided that the above copyright *
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* * notice appear in all copies. The University of California *
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* * makes no representations about the suitability of this *
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* * software for any purpose. It is provided "as is" without *
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* * express or implied warranty. Export of this software outside *
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* * of the United States of America may require an export license. *
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* *********************************************************************
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*
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*/
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#ifndef _MAGIC__EXTRACT__EXTRACT_H
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#define _MAGIC__EXTRACT__EXTRACT_H
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#include "utils/magic.h"
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#include "database/database.h" /* TileTypeBitMask */
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/* Extractor warnings */
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#define EXTWARN_DUP 0x01 /* Warn if two nodes have the same name */
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#define EXTWARN_LABELS 0x02 /* Warn if connecting to unlabelled subcell
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* node.
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*/
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#define EXTWARN_FETS 0x04 /* Warn about badly constructed fets */
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#define EXTWARN_ALL (EXTWARN_DUP|EXTWARN_LABELS|EXTWARN_FETS)
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extern int ExtDoWarn; /* Bitmask of above */
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/* Known devices (see ExtTech.c and ExtBasic.c) */
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/* Make sure these match extDevTable in extract/ExtBasic.c and */
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/* also extflat/EFread.c */
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#define DEV_FET 0 /* FET w/area, perimeter declared */
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#define DEV_MOSFET 1 /* FET w/length, width declared */
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#define DEV_ASYMMETRIC 2 /* Like MOSFET but D,S not swappable */
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#define DEV_BJT 3 /* Bipolar Junction Transistor */
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#define DEV_RES 4 /* Resistor */
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#define DEV_CAP 5 /* Capacitor */
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#define DEV_CAPREV 6 /* Capacitor, terminals reversed */
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#define DEV_VOLT 7 /* Voltage source (used for shorts) */
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#define DEV_DIODE 8 /* Diode */
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#define DEV_PDIODE 9 /* pDiode, same as Diode */
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#define DEV_NDIODE 10 /* nDiode, terminals reversed */
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#define DEV_SUBCKT 11 /* general-purpose subcircuit */
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#define DEV_RSUBCKT 12 /* Resistor-like subcircuit. */
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#define DEV_MSUBCKT 13 /* MOSFET-like subcircuit. */
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#define DEV_CSUBCKT 14 /* Capacitor-like subcircuit. */
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#define DEV_VERILOGA 15 /* Verilog-A model ("N" component) */
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/* Device names for .ext file output (new in version 7.2) */
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/* (defined in extract/ExtBasic.c *and* extflat/EFread.c) */
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extern const char * const extDevTable[];
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/* Extractor options */
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#define EXT_DOADJUST 0x001 /* Extract hierarchical adjustments */
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#define EXT_DOCAPACITANCE 0x002 /* Extract capacitance */
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#define EXT_DOCOUPLING 0x004 /* Extract coupling capacitance */
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#define EXT_DORESISTANCE 0x008 /* Extract resistance */
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#define EXT_DOLENGTH 0x010 /* Extract pathlengths */
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#define EXT_DOFRINGEHALO 0x020 /* Distributed fringe capacitance */
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#define EXT_DOALL 0x03f /* ALL OF THE ABOVE */
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#define EXT_DOLABELCHECK 0x040 /* Check for connections by label */
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#define EXT_DOALIASES 0x080 /* Output all node aliases */
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extern int ExtOptions; /* Bitmask of above */
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extern char *ExtLocalPath; /* If non-NULL, location to write .ext files */
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/* Options for "extract unique" */
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#define EXT_UNIQ_ALL 0
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#define EXT_UNIQ_TAGGED 1
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#define EXT_UNIQ_NOPORTS 2
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#define EXT_UNIQ_NOTOPPORTS 3
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extern bool ExtTechLine();
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extern void ExtTechInit();
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extern void ExtTechFinal();
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extern void ExtSetStyle();
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extern void ExtPrintStyle();
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extern void ExtSetPath();
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extern void ExtPrintPath();
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extern void ExtRevertSubstrate();
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extern Plane *ExtCell();
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extern void ExtractOneCell();
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extern int ExtGetGateTypesMask();
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extern int ExtGetDiffTypesMask();
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#ifdef MAGIC_WRAPPER
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extern bool ExtCompareStyle();
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#endif
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#ifdef THREE_D
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extern void ExtGetZAxis();
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#endif
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extern void ExtDumpCaps();
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extern int extEnumTilePerim(Tile *tpIn, const TileTypeBitMask *maskp, int pNum, int (*func)(), ClientData cdata);
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extern Plane *extPrepSubstrate();
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/* C99 compat */
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extern void ExtAll();
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extern void ExtIncremental();
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extern void ExtLengthClear();
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extern void ExtParents();
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extern void ExtSetDriver();
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extern void ExtSetReceiver();
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extern void ExtShowParents();
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extern void ExtTechScale();
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extern void ExtUnique();
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extern void ExtractTest();
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extern int ExtFindNeighbors();
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extern void ExtFreeLabRegions();
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extern void ExtResetTiles();
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extern void extArray();
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extern void extFindCoupling();
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extern void extHierAdjustments();
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extern void extHierConnections();
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extern void extHierFreeLabels();
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extern void extHierFreeOne();
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extern void extHierFreeOne();
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extern void extHierSubstrate();
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extern int extHierYankFunc();
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extern bool extLabType();
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extern void extLength();
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extern void extLengthInit();
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extern void extOutputConns();
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extern void extOutputCoupling();
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extern int extPathTileDist();
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extern void extRelocateSubstrateCoupling();
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extern void extSetNodeNum();
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extern void extShowTile();
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extern void extSubtree();
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extern int extUniqueCell();
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extern void ExtLabelOneRegion();
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extern void ExtInit();
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extern bool ExtGetDevInfo();
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#endif /* _MAGIC__EXTRACT__EXTRACT_H */
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