traditionally been kept for backwards compatibility. However, the
operation of "ext2spice" and "ext2sim" as separate programs has
become extremely difficult to maintain, and so it has been dropped
in favor of folding both into the program as commands, as was done
a long time ago in the Tcl/Tk version.
file to generate a mask of all the types called out in the section
as being used for parasitic calculations (resistive and capacitive)
and device terminal types. This is supplemented with a list of all
types that are specified in the "connect" and "contact" sections as
connecting to something other than themselves. All remaining types
are considered non-electrical and removed from the list of types
that can be considered electrical nodes. This works a bit better
than the existing method of using "resist <types> None" to specify
non-electrical types, as it is backwardly-compatible to older tech
files. The upshot is that in the worst case, if a type needs to be
extracted as an electrical node but does not satisfy any of the
above criteria, then it should be added to the "resist" list, with
a resistance of 0 if necessary.
"defaultareacap" and "defaultperimeter" statements in the technology
file. Now, the parser makes use of the configuration of the
substrate from the "substrate" line to generate a default list of
which types and planes represent the substrate, and which types and
planes represent shielding to the substrate. This solves an issue
with the use of substrate isolation layers (e.g., "isosub" in
sky130A), because its definition and usage created substrate shields
on two planes (well and dwell), while the syntax for "defaultareacap"
and "defaultperimeter" only allow one shielding plane to be defined.
clean up memory after running "ext2spice". There are apparently
still memory leaks somewhere, difficult to diagnose with valgrind,
but this fix removes the most substantial leakage and allows
"ext2spice" to be run continuously, at least for a while.
to be scaled twice when using the "extract style" command and with an
extraction style that uses micron units. The microns-to-internal
units conversion expects an unscaled result when calling
CIFGetOutputScale(), but except when loading a tech file for the
first time, this value is scaled, and causes the double scaling.
Fixed by unscaling the CIF output before reloading the extraction
style, then scaling it afterward.
necessarily a 1:1 correspondence from tile types to extracted
device names, and not necessarily a 1:1 correspondence in the other
direction, either. So the search for devices at the location given
by the .sim file has been loosened to look for any tile type at that
location. Matches are restricted to those in which the plane of the
type found is the same as the plane of the device recorded in the .sim
file; this prevents matching device like MiM caps that may be in the
same location as a device in another plane.
recursive loop and crash magic. Corrected a number of other issues
along the way, especially one where routines in EFantenna and extresist
make use of array EFDevTypes which was only created by ext2sim and
ext2spice, and freed when done. Having run extresist through valgrind,
there are still issues in the code.
asymmetric MOSFET definitions in the tech file "extract" section.
Corrected the nmos.tech.in file to put the resistance classes in
plane order, as otherwise the interpretation of which resistance
classes belongs to the transistor source and drain can get messed
up by the presence of buried contacts.
p device; this was previously dependent only on the first character
of the extracted device model name. Since the tech file has control
over what the device layer names are but not the extracted model
names, the device layer type name is used as a backup way to determine
if the type is n or p, if that cannot be determined from the extracted
model name.
support asymmetric FETs and other devices like bipolars that have
three distinct terminals. This does not go as far as it should to
make the array independent of the number of declared terminals of
the device. However, it suffices to make, e.g., parameter "a2=area"
work for a bipolar device, and to generate the right drain and source
areas and perimeters for asymmetric (e.g., extended-drain) devices.
works for the first pair of types/plane being below the second pair of
types/plane (upward fringing from the top of a wire to an overlapping
wire above it), which was not being handled due to an implicit assumption
that plane1 < plane2, which does not have to be the case.
could cause serious errors on systems that do not auto-zero allocated
memory. Also: Fixed an error introduced by a recent commit to allocate
character memory for efReadLine() which frees the memory before reading
a .res.ext file, causing a crash when using "ext2spice" with the
"extresist on" option.
optional name field to the "substrate" line in the extract section
of the techfile. This is the default name of the substrate if not
connected to anything labeled. It may use a Tcl variable (preferred).
(2) Added command option "instance orientation [-def]" that returns
the orientation of the named or selected instance. The -def option
returns the orientation using DEF naming convention; otherwise, the
naming used with "getcell" is generated.
areas and writes ANTENNAGATEAREA and ANTENNADIFFAREA values.
(2) Determines "USE POWER" or "USE GROUND" from label names
matching Tcl variables $VDD and $GND, if the USE has not been
registered as a cell property (knowning the use allows magic
to avoid writing an ANTENNADIFFAREA for power rails, although
doing so should not be an issue).
Conflicts:
VERSION
database/DBcellsrch.c
database/DBconnect.c
extract/ExtInter.c
lef/Depend
utils/Depend
Updated bplane branch with all changes to master since the bplane branch
was last modified.
include (1) specification of sidewall or surface to use for
each type individually, rather than a single method for all
types, and (2) specification of a linear model R = Ax + B for
the ratio limit when diodes are attached to the wire, where x
is the diode surface area (unitless, as this is a ratio).
checks. Added new command "antennacheck" and a routine that
adds feedback entries where violations are found. Extended the
syntax of the extraction section of the techfile to support the
antenna ratios and antenna calculation methods.
perimeter were not output because of recent code that broke the
routine that assigns the resistance classes to devices. This is
now fixed. Thanks to Dan Moore for bringing this to my attention,
and debugging investigations.
principle layer name, which should not happen (especially in the
case of space, where layers may be aliased to "space" to make them
ignored on input). Also: Implemented a "-<types>" option to the
"substrate" record in the techfile to declare types which shield
layers from the substrate. This allows types like pwell to be used
in different contexts, e.g., as part of the substrate, or as a P-well
in deep N-well, without requiring a different type. This works in
conjunction with the recently-implemented "+<types>" ID types for
devices. All of this may seem unnecessary but helps to reduce the
number of layers needing to be defined, and the subsequent complexity
of the DRC rulesets.
to be more robust and not depend on the ordering of the devices in
the techfile. The extraction method now keeps a mask of which
properties of the device (source/drain types, substrate type,
identifier type) have been found, and will look only for device
records that match what is known about the device. Added a device
identifier record which is the last record before parameters if the
record begins with "+". This allows marker layers to be placed
over a device such that it will extract with a different type.
This helps reduce the complexity of the techfile and allows
certain specialized devices like RF or ESD to be identified without
a separate layer type for the device.
extraction times, which is an incorrect units conversion of the
"step" parameter in the extract section. It was converting based
on the "lambda" parameter in the same section, which has to do with
the scaling of values in the output file, not the scale factor of
the database to be extracted, which is set by the current CIF output
scale. Once fixed, extraction times are minimized using the rule of
thumb mentioned in the techfile reference, which is 50 times the
minimum feature size. Also: Give the lengthy nature of extraction
on large designs no matter how well optimized, added a feature to
mark the progress of the extraction in increments of 5%. Does not
output progress for small cells that extract quickly.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
development had been halted since it was first created back in April.
Version 8.2 is now the official development version, with the first
development push to create a Cairo graphics interface.
Tim Edwards