Commit Graph

14 Commits

Author SHA1 Message Date
Tim Edwards 8e22b1504e Corrected an error introduced with the extension of extraction methods
to multiple entries per device;  the resistor length and width calculating
routine lost a break statement and would go into an infinite loop for
resistors with bends in them.
2019-11-13 14:29:19 -05:00
Tim Edwards 3a6f868efc Corrected an error in ext2spice caused by recent changes, that can
generate an extra node in the extract output that comes out as a
"(none)" node in the SPICE netlist from ext2spice.
2019-11-13 13:05:03 -05:00
Tim Edwards b0719384e4 Modified the new extraction method with multiple records for each
device type so that it is now properly backwards compatible with
the old-style "fet" records.  Also corrected the record matching
such that it properly matches according to the number of terminals
while allowing the traditional interpretation that there may be
fewer S/D type records than terminals if the S/D types are the
same for all terminals.
2019-10-14 11:09:58 -04:00
Tim Edwards 4b5566af3e Corrected an error that causes alias names for layers to become the
principle layer name, which should not happen (especially in the
case of space, where layers may be aliased to "space" to make them
ignored on input).  Also:  Implemented a "-<types>" option to the
"substrate" record in the techfile to declare types which shield
layers from the substrate.  This allows types like pwell to be used
in different contexts, e.g., as part of the substrate, or as a P-well
in deep N-well, without requiring a different type.  This works in
conjunction with the recently-implemented "+<types>" ID types for
devices.  All of this may seem unnecessary but helps to reduce the
number of layers needing to be defined, and the subsequent complexity
of the DRC rulesets.
2019-09-18 20:48:33 -04:00
Tim Edwards 63829cbbaa Hopefully final correction to new extraction method. Now correctly
handles diodes or other devices with source/drain on planes other
than the plane of the device type.  This no longer requires that
the non-connecting type be in any given terminal position.  The
device type boundary is surveyed for all types, connecting or
overlapping, and at least one of each required type must be present.
2019-08-24 14:18:03 -04:00
Tim Edwards 9f973fa9fc Minor correction to device extraction using the new device structure
format with multiple devices per magic tile type.  The code was left
incompatible with diodes defined with one terminal as substrate
(and therefore no source/drain-like types connecting to the device
type).  This has been fixed.
2019-08-23 14:01:28 -04:00
Tim Edwards 942eaf8113 Revised the substrate extraction method: Instead of searching on
all types specified in the "substrate" statement, split such types
into those on the declared well plane, and everything else.  Any
types on the well plane are searched as before.  Types not on the
well plane (e.g., psd on active) are searched and added to the
substrate node *only* if overlapping nothing on the well plane.
This allows a type such as "psd" to be used on, e.g., both space
(substrate) and deep pwell, but only be extracted as part of the
substrate when found over space.  Note that if there is NO
implicit substrate, the substrate connections will always be
found through the usual connection rules.
2019-08-20 08:42:07 -04:00
Tim Edwards 8c75f81cc4 Revised the method for multiple extraction models per device type
to be more robust and not depend on the ordering of the devices in
the techfile.  The extraction method now keeps a mask of which
properties of the device (source/drain types, substrate type,
identifier type) have been found, and will look only for device
records that match what is known about the device.  Added a device
identifier record which is the last record before parameters if the
record begins with "+".  This allows marker layers to be placed
over a device such that it will extract with a different type.
This helps reduce the complexity of the techfile and allows
certain specialized devices like RF or ESD to be identified without
a separate layer type for the device.
2019-08-19 14:11:02 -04:00
Tim Edwards 25304924b7 Corrected an apparently long-standing (but relatively obscure) error
where devices extracted as "device resistor" or "device capacitor"
and defining parameters (e.g., area, perimeter) will generate the
device arguments in the wrong order in the .ext file, resulting in
incorrect readback when attempting to do ext2spice, resulting in the
device being omitted from the resulting netlist.
2019-01-30 17:16:50 -05:00
Tim Edwards 6f8ec21a11 Two improvements: (1) Command extension "ext2spice lvs" sets up
all the settings normally used for LVS (hierarchy on, cthresh
infinite, subcircuit top auto, etc.).  (2) Extract and extract
unique ignore cells marked as abstract views (property LEFview
is set) when checking for unconnected nets with the same name
label.
2018-10-31 14:33:24 -04:00
Tim Edwards e20319f3c1 Corrected an error in the last commit that causes serious problems
in the SPICE netlist when using new device "csubcircuit" due to
a mismatch in the expected number of parameters.  However, more
work needs to be done to cover capacitor top and bottom plates on
different planes.
2018-10-30 17:17:49 -04:00
Tim Edwards 7dc15a7d28 Added extraction device type "csubcircuit", which should have been
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
2018-10-30 16:19:20 -04:00
Tim Edwards 088fc759c4 Set of changes updating version 8.2 to the level of 8.1, since 8.2
development had been halted since it was first created back in April.
Version 8.2 is now the official development version, with the first
development push to create a Cairo graphics interface.
2017-08-01 22:14:42 -04:00
Tim Edwards 231a299b16 Initial commit at Tue Apr 25 08:41:48 EDT 2017 by tim on stravinsky 2017-04-25 08:41:48 -04:00