limit of the Calma definition, and probably has not done so for ages.
Nobody informed me of this. The restriction has been lifted from
GDS input and output in Magic. It can be reinstated if necessary by
setting a flag in the cifoutput section of the techfile, but it is
likely that this will not be necessary unless there are other tools
that enforce the limit and will not read a GDS file that exceeds it.
the right argument type (float, not int). Otherwise all resistances
from extresist come out zero when doing "ext2spice extresist on"
and "ext2spice hierarchy on". Also changed the format of the resistance
in the SPICE output to type float, since values are in standard units of
ohms, and rounding to the nearest ohm seems excessively coarse-grained.
a long-standing error (introduced with the "extresist geometry"
option) that can cause nets not to be extracted (due to the first
record not having extraction data, which was itself a long-standing
error in the code but which was not fixed correctly); (2) handle
"device mosfet" type transistors (previously only handled the old
"fet" type extraction devices); and (3) correct for the res.ext
file having a different scalefactor relative to the .ext file. The
latter item was solved by forcing all input to scale like
ExtCurStyle->exts_unitsPerLambda, locally correcting all input as
needed. Note that extresist still needs to handle other extraction
devices (e.g., resistors and capacitors) but those will require
additional handling in the routines which analyze the current path
to determine how to break up wires into paths.
include (1) specification of sidewall or surface to use for
each type individually, rather than a single method for all
types, and (2) specification of a linear model R = Ax + B for
the ratio limit when diodes are attached to the wire, where x
is the diode surface area (unitless, as this is a ratio).
an existing cell. If the existing cell has labels but the labels
are defined as point labels (no rectangle defined using specific
layer-purpose pairs), then the LEF macro's port geometry will be
used for the labels. Because the GDS file can define label sizes
and fonts, which the LEF file cannot, but because the LEF file may
define multiple rectangles per port, the original point label is
given the first port rectangle from the LEF file, while the
remainder of the labels in the LEF file generate new non-rendered
labels in the cell.
which takes the existing generated CIF plane, finds all enclosed
areas that have an area less than <area>, and fills them in. This
satisfies a minimum hole area rule in a way that is not possible
with any of the existing CIF operators.
which adds an offset value of "start" to both X and Y from the
lower left corner of the fill area. This allows the use of the
"offset" (from the previous git commit) to be declared on different
layers without creating an exact overlap, as is often required by
foundries for fill patterns.
from a selection, which can then be used to index into other lists.
This lets one selection be made on a list of arbitrary names, and
then additional parameters can be linked together with the same
index). Also, implemented (finally!) the "offset" parameters of
the "slots" function (as advertised in the documentation).
like resistors where a tile other than space may border the resistor
device on its non-terminal sides (which is handled correctly, and
should not be considered an error).
remove redundant ports. A comment that I left in the code at the
last commit asked if it was necessary to call efAddNodes and
efAddConns recursively. An example came up in which the answer
is apparently "yes". These routines have been replaced by
efFlatNodes(), which appears to solve the problem. There is now
a question of whether efFlatNodesDeviceless() does anything, and
should its main behavior (to flag deviceless subcircuits) be
folded into efFlatNodes.
categorized by error type and scrolled through conveniently. However,
it needs work dealing with finding the actual error bounds. The
"DRC count" counts tiles, which is tile-plane-geometry-specific, and
"DRC listall why" fractures errors both over tiles and over the square
areas that the interactive DRC splits the layout into, for performance.
The DRC error plane needs to be changed to hold different types for
each error class, so that errors can be scanned by boundary instead of
by tile (work to be done).
rid of redundant port entries in subcircuits. There is still an outstanding
issue as to whether nodes and connections need to be recursively iterated
to the hierarchy bottom. The current fix corrected the test case. Also,
added a "-dereference" option to the "load" command to revert to the
original behavior of using only search paths from "addpath" when searching
for files to load.
Tim Edwards