only at the time of running the command "load". But cells are generally
loaded only on an as-needed basis, so the dereferencing option must be
saved as a flag in the cell and honored whenever its subcells are expanded
or otherwise read at a later time.
include (1) specification of sidewall or surface to use for
each type individually, rather than a single method for all
types, and (2) specification of a linear model R = Ax + B for
the ratio limit when diodes are attached to the wire, where x
is the diode surface area (unitless, as this is a ratio).
like resistors where a tile other than space may border the resistor
device on its non-terminal sides (which is handled correctly, and
should not be considered an error).
rid of redundant port entries in subcircuits. There is still an outstanding
issue as to whether nodes and connections need to be recursively iterated
to the hierarchy bottom. The current fix corrected the test case. Also,
added a "-dereference" option to the "load" command to revert to the
original behavior of using only search paths from "addpath" when searching
for files to load.
to multiple entries per device; the resistor length and width calculating
routine lost a break statement and would go into an infinite loop for
resistors with bends in them.
checks. Added new command "antennacheck" and a routine that
adds feedback entries where violations are found. Extended the
syntax of the extraction section of the techfile to support the
antenna ratios and antenna calculation methods.
perimeter were not output because of recent code that broke the
routine that assigns the resistance classes to devices. This is
now fixed. Thanks to Dan Moore for bringing this to my attention,
and debugging investigations.
device type so that it is now properly backwards compatible with
the old-style "fet" records. Also corrected the record matching
such that it properly matches according to the number of terminals
while allowing the traditional interpretation that there may be
fewer S/D type records than terminals if the S/D types are the
same for all terminals.
principle layer name, which should not happen (especially in the
case of space, where layers may be aliased to "space" to make them
ignored on input). Also: Implemented a "-<types>" option to the
"substrate" record in the techfile to declare types which shield
layers from the substrate. This allows types like pwell to be used
in different contexts, e.g., as part of the substrate, or as a P-well
in deep N-well, without requiring a different type. This works in
conjunction with the recently-implemented "+<types>" ID types for
devices. All of this may seem unnecessary but helps to reduce the
number of layers needing to be defined, and the subsequent complexity
of the DRC rulesets.
handles diodes or other devices with source/drain on planes other
than the plane of the device type. This no longer requires that
the non-connecting type be in any given terminal position. The
device type boundary is surveyed for all types, connecting or
overlapping, and at least one of each required type must be present.
format with multiple devices per magic tile type. The code was left
incompatible with diodes defined with one terminal as substrate
(and therefore no source/drain-like types connecting to the device
type). This has been fixed.
all types specified in the "substrate" statement, split such types
into those on the declared well plane, and everything else. Any
types on the well plane are searched as before. Types not on the
well plane (e.g., psd on active) are searched and added to the
substrate node *only* if overlapping nothing on the well plane.
This allows a type such as "psd" to be used on, e.g., both space
(substrate) and deep pwell, but only be extracted as part of the
substrate when found over space. Note that if there is NO
implicit substrate, the substrate connections will always be
found through the usual connection rules.
to be more robust and not depend on the ordering of the devices in
the techfile. The extraction method now keeps a mask of which
properties of the device (source/drain types, substrate type,
identifier type) have been found, and will look only for device
records that match what is known about the device. Added a device
identifier record which is the last record before parameters if the
record begins with "+". This allows marker layers to be placed
over a device such that it will extract with a different type.
This helps reduce the complexity of the techfile and allows
certain specialized devices like RF or ESD to be identified without
a separate layer type for the device.
where devices extracted as "device resistor" or "device capacitor"
and defining parameters (e.g., area, perimeter) will generate the
device arguments in the wrong order in the .ext file, resulting in
incorrect readback when attempting to do ext2spice, resulting in the
device being omitted from the resulting netlist.
extraction times, which is an incorrect units conversion of the
"step" parameter in the extract section. It was converting based
on the "lambda" parameter in the same section, which has to do with
the scaling of values in the output file, not the scale factor of
the database to be extracted, which is set by the current CIF output
scale. Once fixed, extraction times are minimized using the rule of
thumb mentioned in the techfile reference, which is 50 times the
minimum feature size. Also: Give the lengthy nature of extraction
on large designs no matter how well optimized, added a feature to
mark the progress of the extraction in increments of 5%. Does not
output progress for small cells that extract quickly.
all the settings normally used for LVS (hierarchy on, cthresh
infinite, subcircuit top auto, etc.). (2) Extract and extract
unique ignore cells marked as abstract views (property LEFview
is set) when checking for unconnected nets with the same name
label.
in the SPICE netlist when using new device "csubcircuit" due to
a mismatch in the expected number of parameters. However, more
work needs to be done to cover capacitor top and bottom plates on
different planes.
added a long time ago, since capacitors use a different method for
calculating width and length than either transistors or resistors,
so subcircuits need a special class designator or else the extraction
may calculate the wrong dimensions for device width by totalling the
perimeter between the device and terminal types, as it would for a
MOSFET.
development had been halted since it was first created back in April.
Version 8.2 is now the official development version, with the first
development push to create a Cairo graphics interface.
Tim Edwards