statements in the .ext file output to those that mark a port as
equivalent to the node name used elsewhere in the file. This
limits unnecessary output of "equiv" statements that can bog down
ext2spice and other commands that use the .ext file contents.
substrate nodes in subcircuits that don't make connections to the
substrate (such as arrays of pFETs). This is done under the
restriction that ext2spice is being called without generating
parasitics (otherwise the connection to substrate is valid), as it
would be when extracting for LVS. The ground node must not appear
as a connection to any device. This is then propagated up the
hierarchy such that if none of a subcell's descendents connect to
the substrate, then neither does the subcell.
previous commit and can cause ports in the SPICE netlist to have
names other than what the port label declared. Expected not to be
fatal to the netlist, but it's a bit difficult to work with a
subcircuit that doesn't have the expected pin names.
specific nets to extract, rather than excluding them. That allows
"extresist" to target specific nets like the power supply or a clock
tree for extraction.
wrong, and it needs revisiting. This is the cause of a number of
negative capacitances appearing in the netlist (even after accounting
for overlap with subcircuits).
this appears to work correctly but does not yet handle the implicit
substrate (space as substrate) or "virtually" isolated substrate regions
(which need to be removed for full parasitic extraction).
all geometry will be handled; the previous behavior expected only
a single rectangle per pin and so would only acknowledge the last
entry in any list of rectangles for the pin.
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file. Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around. This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
"ext2sim extresist on", which was being shared; that leads to
confusion, especially when using "ext2sim" to generate a node
name input file for "extresist". Also: Added a warning when two
ports are merged in a .ext file, as this can lead to numerous
incorrect entries in netlist output.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
to be scaled twice when using the "extract style" command and with an
extraction style that uses micron units. The microns-to-internal
units conversion expects an unscaled result when calling
CIFGetOutputScale(), but except when loading a tech file for the
first time, this value is scaled, and causes the double scaling.
Fixed by unscaling the CIF output before reloading the extraction
style, then scaling it afterward.
to copy up errors from non-interacting subcells. The routine was
only copying up TT_ERROR_P type errors, but for deep hierarchies,
TT_ERROR_S type errors may have to be propagated up as well.
Tim Edwards
Harald Pretl
Harald Pretl
Ryan Schmidt
Sai Charan Lanka
Sai Charan Lanka