of an existing cell, which does not appear to be a fatal problem,
but must be causing a memory leak. Also: Corrected an error in
extresist when reading .sim files, in code that is slated to be
overhauled, so this is just a patch to avoid a crash condition.
1) Corrected spurious error messages about cells already existing
in GDS when using "flatten" or "flatglob".
2) Fixed handling of resistance as a subcircuit parameter
3) Added area and perimeter resistance for a device; this is done
through the "devresist" statement in the tech file, which is an
extension of the original "fetresist" statement. Where "fetresist"
only supported type "linear", "devresist" supports types "area"
and "perimeter".
4) Support for CDL syntax, including generating subcircuit-like
parameters for components starting with SPICE-standard prefixes
like M, R, C, etc., adding "/" between pins and subcircuit name,
and saving the file as ".cdl" instead of ".spice".
5) Estimated L and W for devices whose geometry is complex and do not
reduce to a simple rectangle. L and W are estimated as the square
root of the area.
6) Changed the method of extracting L and W for diodes to use the same
method as capacitors. Note that diodes are not usually specified
by L and W, but if they are, this will produce the right result.
7) Corrected the reported filename and line number when printing error
messages related to errors inside a technology file, when the
technology file uses "include" to combine multiple files.
After futher review of this function it looks like the existing
fclose() is not in the correct place, and recent patches have
added fclose() to this function in better places (covering all
returns) but did not take into account the existing misplaced
fclose().
Guided by CodeQL static code analyser.
FileMayNotBeClosed.ql
FileMayNeverBeClosed.ql
The trick with "if(fp != stdout)" is problematic (to analyser) as
technically 'stdout' can be a global pointer that COULD be modified any
time, so it might have changed between the fopen() and fclose() calls so
the close MAY NEVER occurs (which is problem the analyzer can see).
So local state is maintained as a bool which will also clarify to the
compiler see the intention without concern for external stdout
modification.
Some items appear to be out and out leaks when certain commands are use.
PlowRules1.c:439:9: warning: suggest parentheses around assignment used as truth value
PlowTech.c:645:17: warning: suggest parentheses around assignment used as truth value
PlowTech.c:652:17: warning: suggest parentheses around assignment used as truth value
PlowTech.c:1019:17: warning: suggest parentheses around assignment used as truth value
ResReadSim.c:270:13: warning: suggest parentheses around assignment used as truth value
ResReadSim.c:871:9: warning: suggest parentheses around assignment used as truth value
ResRex.c:1840:17: warning: suggest parentheses around assignment used as truth value
getrect.c:72:9: warning: suggest parentheses around assignment used as truth value
getrect.c:79:9: warning: suggest parentheses around assignment used as truth value
getrect.c:86:9: warning: suggest parentheses around assignment used as truth value
getrect.c:93:9: warning: suggest parentheses around assignment used as truth value
hash.c:732:16: warning: suggest parentheses around assignment used as truth value
heap.c:328:17: warning: suggest parentheses around assignment used as truth value
heap.c:344:17: warning: suggest parentheses around assignment used as truth value
netlist.c:323:17: warning: suggest parentheses around assignment used as truth value
niceabort.c:121:9: warning: suggest parentheses around assignment used as truth value
path.c:1102:12: warning: suggest parentheses around assignment used as truth value
pathvisit.c:245:13: warning: suggest parentheses around assignment used as truth value
pathvisit.c:295:17: warning: suggest parentheses around assignment used as truth value
tech.c:656:17: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1591:16: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1622:16: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1813:12: warning: suggest parentheses around assignment used as truth value
ext2spice.c:1862:12: warning: suggest parentheses around assignment used as truth value
ext2spice.c:3808:16: warning: suggest parentheses around assignment used as truth value
CalmaRdio.c:437:9: warning: suggest parentheses around assignment used as truth value
CalmaWrite.c:396:9: warning: suggest parentheses around assignment used as truth value
CalmaWrite.c:1772:29: warning: suggest parentheses around assignment used as truth value
CalmaWriteZ.c:372:9: warning: suggest parentheses around assignment used as truth value
CalmaWriteZ.c:1608:29: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:209:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:214:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:220:9: warning: suggest parentheses around assignment used as truth value
CIFrdtech.c:226:9: warning: suggest parentheses around assignment used as truth value
CIFrdutils.c:1258:12: warning: suggest parentheses around assignment used as truth value
GCC14 -Wall cleanup series [-Wparentheses]
command for use with "extract path"; the cellname was being cleared
after generating the filename with the extract path, but was being
used afterward, so it needed to be reverted back to the original
value, not just free'd. Otherwise "extresist" will fail to produce
any results.
encountered an issue where a label in a flattened layout
exceeded 256 characters, ended up in the .sim file, and was
truncated when read back during "extresist". The change to 1024
is a stop-gap measure because ultimately I want to replace the
use of .sim files with .ext files using the routines in extflat/,
which would deprecate everything in ResReadSim.c.
isolate the terminal areas of a device (e.g., source and drain)
and calculate their area and perimeter individually for the
device (in addition to the traditional method of calculating
area and perimeter of each resistance class for the entire node).
Also: Reworked the SPICE syntax output to generate SI values
in the range 1-1000 with the appropriate suffix (e.g., "20u")
instead of defaulting to "u" for lengths and "p" for areas.
This prevents it from producing weird units like "150000u" when
a process definition already includes a scalefactor.
Reworked the "extresist" code to use the device terminal area
and perimeter. This fixes an error in which "extresist" would
lose these values and "ext2spice" with option "extresist on"
would generate a new netlist output with zero terminal areas
and perimeters.
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file. Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around. This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
the last commit, unfortunately. Thanks to Matt Guthaus for alerting me
to this. Also updated parts of the extresist code that remove the
dependence on ResConDCS; this is a minor update and should not affect
the operation of extresist. It is preparatory to doing more work to
support additional device types like capacitors, bipolars, and diodes.
extresist extractor is less sophisticated than the standard extraction
and will not check through the list of device records belonging to a
single device type. Therefore a device in the .res.ext may have a
different device name. So name hashing and checks are made against
the tile type, not the device name, as the tile type + device
coordinates is sufficient to uniquely identify the device. However,
the extresist extractor does need to be sophisticated enough to find
all the terminal types, so that needs to be fixed.
recursive loop and crash magic. Corrected a number of other issues
along the way, especially one where routines in EFantenna and extresist
make use of array EFDevTypes which was only created by ext2sim and
ext2spice, and freed when done. Having run extresist through valgrind,
there are still issues in the code.
commit, mostly relating to the scale of values in the ".nodes" file
produced by ext2sim. Making this file CIF syntax seemed unnecessary,
so I removed the CIF syntax and scaling. "extresist" can now produce
an apparently valid output on a standard cell layout. Even with the
change, the extresist output is still only pseudo-hierarchical, so
this does not preclude the need for eliminating the .sim format file
in favor of the .ext file, but it provides a working intermediate
form.
types and substrate connections. This is an intermediate step to
switching from a sim file format to an ext file format for input,
but resolves the worst issues of having the sim file not recognize
the devices or the substrate nodes. Implemented by using the sim
subcircuit format introduced in IRSIM with the "user subcircuit"
package. Implementation unfinished (work in progress).
a long-standing error (introduced with the "extresist geometry"
option) that can cause nets not to be extracted (due to the first
record not having extraction data, which was itself a long-standing
error in the code but which was not fixed correctly); (2) handle
"device mosfet" type transistors (previously only handled the old
"fet" type extraction devices); and (3) correct for the res.ext
file having a different scalefactor relative to the .ext file. The
latter item was solved by forcing all input to scale like
ExtCurStyle->exts_unitsPerLambda, locally correcting all input as
needed. Note that extresist still needs to handle other extraction
devices (e.g., resistors and capacitors) but those will require
additional handling in the routines which analyze the current path
to determine how to break up wires into paths.
with ext2spice without the hierarchy option. More work needed to
produce correct hierarchical output and to support extraction
devices other than the old "fet" record.
simple FET device in extresist. Also: Extended the bloat-all CIF operator
again, allowing the trigger layer for the bloat operation to include both
CIF layers and magic layers (previously only magic layers were supported).
This extension is possible due to the previous extension allowing the
trigger layer and bloating layers to be on separate planes. This operator
extension is useful for tagging geometry that is in the proximity of, but
not overlapping, geometry on another plane.
hierarchical cells (namely a scaling issue with .sim file units).
More can be done to make the extresist command more user friendly,
but at least port connections as drivers appears to work.
to be more robust and not depend on the ordering of the devices in
the techfile. The extraction method now keeps a mask of which
properties of the device (source/drain types, substrate type,
identifier type) have been found, and will look only for device
records that match what is known about the device. Added a device
identifier record which is the last record before parameters if the
record begins with "+". This allows marker layers to be placed
over a device such that it will extract with a different type.
This helps reduce the complexity of the techfile and allows
certain specialized devices like RF or ESD to be identified without
a separate layer type for the device.
R. Timothy Edwards
Darryl L. Miles