because otherwise all pins will flag metal-to-obstruction spacing
within the cell if the cell is wide enough that the obstruction
layer satisfies the width requirement for the rule. It is too
complicated to try to find specific places where the wide spacing
might not be needed. Potentially this could be a problem for
technologies that define a number of graded wide-spacing rules,
as the largest-width rule is always used now by "lef write -hide",
and the largest-width rule could theoretically allow enough space
to route through, which would cause a short that cannot be
detected. That would be a pathological case that may not show up
in practice.
labels by expanding a zero area label rectangle, but then if "select
chunk" returns nothing, it sets the area to the zero area label
rectangle instead of the expanded one that it just created. This
is the reason that "lef write" is producing pins with no geometry
in the LEF file output.
not useful so long as Tcl_Alloc() has (unsigned int) for an argument.
The more important investigation is probably to determine if there is
a way to keep csa2_list from growing to absurdly large sizes on
connectivity checks.
magic crashed when the conSrArea array exceeded the size of a 32-bit
int during the antenna rule check. Should be good for another four
orders of magnitude.
the last couple of days, was left in a state where it keeps appending
".mag" to the filename if "save" or "writeall" is executed more than
once in the same edit session. Also, added ext2sim.sh and ext2spice.sh
to the CLEANS list in tcltk, and added both to .gitignore so they are
not tracked. Removed them from git to stop the current tracking.
as an optional argument (which it is), and so defaults were not
applied, potentially leading to the wrong number of rows/columns in
a generated via if ROWCOL is not present in the DEF file.
of the pin port geometry and using those areas to create the
spacing between them and the obstruction layer. Otherwise, the
existing method used different databases (source vs. flattened) to
find the pin area, and they did not always agree on the exact
dimensions, leading to spacing errors within the LEF view.
than one name, because in that case one of the port records ends
up with a null pointer to a node, and causes a crash condition.
This can happen inadvertently, as when a connected node is not
specifically designated a port, but is forced to be a port
because of the connection.
coordinate system origin to the specified (current) location.
This is a much more efficient method than selecting everything in
a layout and moving it, especially for very large layouts where
selection and moving becomes prohibitive.
generating duplicate devices that may have parts overlaid in
different subcells; this failed to filter the check by plane of
the device, and so if any two devices exist at the same point in
two different planes (e.g., metal resistor and a transistor), one
of them would get eliminated.
multiple ports; also, when using the "-hide" option, the obstruction
area is computed from layer geometry, not from the bounding box.
Still left to do: Ensure minimum width on pins, and remove slivers
of obstruction that are below minimum width.
substrate more than once for the same subcell, since the substrate
extraction method scans the entire plane area; this was making
large standard cell layouts extract very slowly, as every component
cell was causing the substrate search to be repeated.
Tim Edwards