statements, with all "hard" connections being enumerated in the
same PORT entry, and "soft" connections (same label on unconnected
areas; e.g., through substrate or resistor device) being
enumerated as separate PORT entries, per the LEF spec. Also
corrected behavior with respect to the "lef write -toplayer"
option, which was treating each port label independently, and so
generating entries for lower layers of a port if there were ports
on those layers, in contravention to the "-toplayer" option.
Also: Added the PINS section to the "def write" output; this had
been left as a "to be completed" item but was never done in spite
of being easy to add.
entries for "floating" labels. Otherwise it is possible for the
hierarchical checks to find the label in flattened geometry and
reference it, resulting in merge statements in an .ext file that
reference undeclared nodes, ultimately resulting in extflat
failing to perform the merge, and an incorrect netlist.
to not get into the subcircuit port list during ext2spice. The new
fix brings back (unfortunately) the behavior of creating a substrate
node for cells that have no substrate connection to any device;
this will have to be handled separately.
solution; it would be much better to make the value adjustible, but
the array of tiles sized to LAYERS_PER_CONTACT is a Region structure,
and the routine that frees the Region structures does not have a way
to call a routine to take additional measures like free'ing a sub-
structure of the Region. A proper solution will require some work.
commands on selections in a cell that is not editable. Moves
and Copies were already handled correctly; this correction fixes
Delete and transforms (e.g., rotates and flips).
messages which was traced to code that changes a drivepoint position
to match a label; the same drivepoint may be part of the record for
the initial position to search on the net, in which case if the
position is changed, then the tile type needs to be changed to match
the new position.
using qsort() instead of its own linked-list-based sorting, which
is horribly inefficient. This change allows power nets (which
tend to be connected to all transistors) to be extracted in a
reasonable amount of time (hours instead of days).
an optional extra argument to the "select" command that can be used
to select labels by glob-style matching; e.g., "select area labels
VSS*" or "select less area labels *_1". This will help in managing
labels after flattening a standard cell design; e.g., by using
"select less area labels */VDD".
to eliminate all redundant names resulting from redundant labels.
Changed the behavior of "goto" so that it will find local names with
slashes, which are the result of using "flatten". A hierarchical
search is done first, as before, but on failure to find a subcell
component, the local cell is searched for the verbatim name.
specific nets to extract, rather than excluding them. That allows
"extresist" to target specific nets like the power supply or a clock
tree for extraction.
wrong, and it needs revisiting. This is the cause of a number of
negative capacitances appearing in the netlist (even after accounting
for overlap with subcircuits).
all geometry will be handled; the previous behavior expected only
a single rectangle per pin and so would only acknowledge the last
entry in any list of rectangles for the pin.
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
"ext2sim extresist on", which was being shared; that leads to
confusion, especially when using "ext2sim" to generate a node
name input file for "extresist". Also: Added a warning when two
ports are merged in a .ext file, as this can lead to numerous
incorrect entries in netlist output.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
to be scaled twice when using the "extract style" command and with an
extraction style that uses micron units. The microns-to-internal
units conversion expects an unscaled result when calling
CIFGetOutputScale(), but except when loading a tech file for the
first time, this value is scaled, and causes the double scaling.
Fixed by unscaling the CIF output before reloading the extraction
style, then scaling it afterward.
to copy up errors from non-interacting subcells. The routine was
only copying up TT_ERROR_P type errors, but for deep hierarchies,
TT_ERROR_S type errors may have to be propagated up as well.
require that an edit cell be defined. This stops a lot of commands
from failing on non-writeable cells. There really should not be a
concept of "non-editable" cells at all, just non-writeable ones.
"|"), pointed out by Jim Everitt. The error is pretty major, but
because the section of code it affects is just eliminating
unnecessary DRC rules, I believe that the only effect is that the
DRC ruleset ends up using more memory than it needs to. But, good
to have fixed.
it is easy to subvert the process by updating GDS without updating
the pointers, it is trivial to end up with bad GDS output. The
sanity checks confirm that the position pointed to is a complete
structure (check begin and end records), and that it has the same
name as the cell (this is not a requirement, as there are reasons
one might want to point to data from a structure of a different
name, but a warning will be printed).
that can be used to force renaming of a read-only cell. The
action revokes the read-only status of the cell and removes any
GDS filename and pointers from the cell's properties. This can be
used to swap out a library cell in a layout for a custom version,
by first forcing a rename of the cell, and then resetting the
filepath of the cell and flushing.
tile corners in the check area to find areas needing bridges.
This prevents generation of unnecessary bridging geometry; and
since the error made the check rotation-dependent, this may
resolve some "parent and child disagree on CIF" errors.
necessarily a 1:1 correspondence from tile types to extracted
device names, and not necessarily a 1:1 correspondence in the other
direction, either. So the search for devices at the location given
by the .sim file has been loosened to look for any tile type at that
location. Matches are restricted to those in which the plane of the
type found is the same as the plane of the device recorded in the .sim
file; this prevents matching device like MiM caps that may be in the
same location as a device in another plane.
very long time but never discovered; in which any implicit port
connection into a subcell (that is otherwise labeled with ports) that
appears at the end of the node list (i.e., after all the declared
ports), will not be output, either in the subcircuit definition or
calls.
presented on the command line, then all following arguments are
assumed to be arguments of the script and not additional input
to be processed by magic. This allows arguments to be passed to
scripts passed to magic on the command line.
is not necessary that the target cell not exist. That allows a
layout to be flattened into a destination in pieces. Also found
that the "flatten" command never frees memory for the CellUse it
creates for the copy, so fixed that as well.
introduced: The use of substitutions for PDKPATH and home directory
in path names for GDS files referenced in abstract views, and the
"gds addendum" option. Both were interfering with magic's handling
of writing GDS files from abstract layout views.
Tim Edwards