that it correctly lands on a grid limit boundary (which the
previous commit did not do). Note that work is still ongoing to
detect some pathological cases where the shapes end up off-grid
where two non-manhattan shapes intersect at different angles
(such as an inside corner).
calculation for "limit" in the CIFgen routines was wrong, not the
interpretation of the "gridlimit" value in the tech file. The
parsing of "gridlimit" has been put back the way it was before the
last commit, and the "limit" value calculations have been corrected.
statements, with all "hard" connections being enumerated in the
same PORT entry, and "soft" connections (same label on unconnected
areas; e.g., through substrate or resistor device) being
enumerated as separate PORT entries, per the LEF spec. Also
corrected behavior with respect to the "lef write -toplayer"
option, which was treating each port label independently, and so
generating entries for lower layers of a port if there were ports
on those layers, in contravention to the "-toplayer" option.
Also: Added the PINS section to the "def write" output; this had
been left as a "to be completed" item but was never done in spite
of being easy to add.
entries for "floating" labels. Otherwise it is possible for the
hierarchical checks to find the label in flattened geometry and
reference it, resulting in merge statements in an .ext file that
reference undeclared nodes, ultimately resulting in extflat
failing to perform the merge, and an incorrect netlist.
reading a bad "bloat-all" statement in a techfile. This prevents
magic from eventually segfaulting when exercising the recipe in which
the bad statement occurs.
to not get into the subcircuit port list during ext2spice. The new
fix brings back (unfortunately) the behavior of creating a substrate
node for cells that have no substrate connection to any device;
this will have to be handled separately.
solution; it would be much better to make the value adjustible, but
the array of tiles sized to LAYERS_PER_CONTACT is a Region structure,
and the routine that frees the Region structures does not have a way
to call a routine to take additional measures like free'ing a sub-
structure of the Region. A proper solution will require some work.
commands on selections in a cell that is not editable. Moves
and Copies were already handled correctly; this correction fixes
Delete and transforms (e.g., rotates and flips).
messages which was traced to code that changes a drivepoint position
to match a label; the same drivepoint may be part of the record for
the initial position to search on the net, in which case if the
position is changed, then the tile type needs to be changed to match
the new position.
using qsort() instead of its own linked-list-based sorting, which
is horribly inefficient. This change allows power nets (which
tend to be connected to all transistors) to be extracted in a
reasonable amount of time (hours instead of days).
an optional extra argument to the "select" command that can be used
to select labels by glob-style matching; e.g., "select area labels
VSS*" or "select less area labels *_1". This will help in managing
labels after flattening a standard cell design; e.g., by using
"select less area labels */VDD".
to eliminate all redundant names resulting from redundant labels.
Changed the behavior of "goto" so that it will find local names with
slashes, which are the result of using "flatten". A hierarchical
search is done first, as before, but on failure to find a subcell
component, the local cell is searched for the verbatim name.
statements in the .ext file output to those that mark a port as
equivalent to the node name used elsewhere in the file. This
limits unnecessary output of "equiv" statements that can bog down
ext2spice and other commands that use the .ext file contents.
substrate nodes in subcircuits that don't make connections to the
substrate (such as arrays of pFETs). This is done under the
restriction that ext2spice is being called without generating
parasitics (otherwise the connection to substrate is valid), as it
would be when extracting for LVS. The ground node must not appear
as a connection to any device. This is then propagated up the
hierarchy such that if none of a subcell's descendents connect to
the substrate, then neither does the subcell.
previous commit and can cause ports in the SPICE netlist to have
names other than what the port label declared. Expected not to be
fatal to the netlist, but it's a bit difficult to work with a
subcircuit that doesn't have the expected pin names.
specific nets to extract, rather than excluding them. That allows
"extresist" to target specific nets like the power supply or a clock
tree for extraction.
wrong, and it needs revisiting. This is the cause of a number of
negative capacitances appearing in the netlist (even after accounting
for overlap with subcircuits).
this appears to work correctly but does not yet handle the implicit
substrate (space as substrate) or "virtually" isolated substrate regions
(which need to be removed for full parasitic extraction).
all geometry will be handled; the previous behavior expected only
a single rectangle per pin and so would only acknowledge the last
entry in any list of rectangles for the pin.
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file. Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around. This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
"ext2sim extresist on", which was being shared; that leads to
confusion, especially when using "ext2sim" to generate a node
name input file for "extresist". Also: Added a warning when two
ports are merged in a .ext file, as this can lead to numerous
incorrect entries in netlist output.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
Tim Edwards
Maximo
Harald Pretl
Harald Pretl