this appears to work correctly but does not yet handle the implicit
substrate (space as substrate) or "virtually" isolated substrate regions
(which need to be removed for full parasitic extraction).
all geometry will be handled; the previous behavior expected only
a single rectangle per pin and so would only acknowledge the last
entry in any list of rectangles for the pin.
actually an issue and probably never relevant. extresist now works
except for substrate connections and soft connections between substrate
regions. That will require additional coding, not bugfixing, so I'm
committing the last of this set of bugfixes before starting that.
(since these are interpreted by IRSIM, the only known program to
parse .sim output)---the "ext2sim alias on" option now just moves
such statements from the ".sim" file to a ".al" file. Corrected the
ResSimMerge() routine to reverse the nodes, so that the devices
belonging to the aliased node are added to the original node, instead
of the other way around. This corrects "missing gate" and "missing SD"
errors that occur due to nodes connected through the substrate.
"ext2sim extresist on", which was being shared; that leads to
confusion, especially when using "ext2sim" to generate a node
name input file for "extresist". Also: Added a warning when two
ports are merged in a .ext file, as this can lead to numerous
incorrect entries in netlist output.
text formatting. Made one critical correction to ResGetDevice() to
pass the device type; otherwise, devices on different planes (e.g.,
MiM caps) with the same coordinate will always return the device on
the lowest plane, leading to incorrect results and an eventual crash
when the device record is free'd twice.
support of devices with terminals on different plances, such as
capacitors, diodes, and bipolar transistors. Output now appears
to give meaningful results for flattened layouts, although
numerous issues remain for hierarchical layouts.
to be scaled twice when using the "extract style" command and with an
extraction style that uses micron units. The microns-to-internal
units conversion expects an unscaled result when calling
CIFGetOutputScale(), but except when loading a tech file for the
first time, this value is scaled, and causes the double scaling.
Fixed by unscaling the CIF output before reloading the extraction
style, then scaling it afterward.
to copy up errors from non-interacting subcells. The routine was
only copying up TT_ERROR_P type errors, but for deep hierarchies,
TT_ERROR_S type errors may have to be propagated up as well.
that commit claimed to correct an issue with implicit ports not being
output, the solution often failed to properly assign the port number,
so while the implicit ports were added to the subcircuit definition,
they were often missing from the subcircuit call.
require that an edit cell be defined. This stops a lot of commands
from failing on non-writeable cells. There really should not be a
concept of "non-editable" cells at all, just non-writeable ones.
"|"), pointed out by Jim Everitt. The error is pretty major, but
because the section of code it affects is just eliminating
unnecessary DRC rules, I believe that the only effect is that the
DRC ruleset ends up using more memory than it needs to. But, good
to have fixed.
it is easy to subvert the process by updating GDS without updating
the pointers, it is trivial to end up with bad GDS output. The
sanity checks confirm that the position pointed to is a complete
structure (check begin and end records), and that it has the same
name as the cell (this is not a requirement, as there are reasons
one might want to point to data from a structure of a different
name, but a warning will be printed).
that can be used to force renaming of a read-only cell. The
action revokes the read-only status of the cell and removes any
GDS filename and pointers from the cell's properties. This can be
used to swap out a library cell in a layout for a custom version,
by first forcing a rename of the cell, and then resetting the
filepath of the cell and flushing.
tile corners in the check area to find areas needing bridges.
This prevents generation of unnecessary bridging geometry; and
since the error made the check rotation-dependent, this may
resolve some "parent and child disagree on CIF" errors.
rules do not get hierarchical processing. I am not sure why I added
that exception, which clearly is not like "bound" or "net" in causing
serious issues when used hierarchically. The current counterexample
is the use in sky130A.tech for the NPC layer. Based on that usage,
the exception has been relaxed to consider any "squares" and similar
rule during hierarchical processing if followed by a "grow" operator.
Possibly this is still not relaxed enough to capture all meaningful
use cases, but should suffice for now.
necessarily a 1:1 correspondence from tile types to extracted
device names, and not necessarily a 1:1 correspondence in the other
direction, either. So the search for devices at the location given
by the .sim file has been loosened to look for any tile type at that
location. Matches are restricted to those in which the plane of the
type found is the same as the plane of the device recorded in the .sim
file; this prevents matching device like MiM caps that may be in the
same location as a device in another plane.
very long time but never discovered; in which any implicit port
connection into a subcell (that is otherwise labeled with ports) that
appears at the end of the node list (i.e., after all the declared
ports), will not be output, either in the subcircuit definition or
calls.
Tim Edwards
Ryan Schmidt
Sai Charan Lanka
Sai Charan Lanka