is placed over multiple types. This causes SelectChunk() to fail
and the pin will have no geometry output in the LEF file. To avoid
this, the area of the label is always painted into the select cell
so that if SelectChunk() fails, the label area still exists with
the label tile type.
(such as widespacing or directional surround) that will cause the
rule to be triggered without a cause due to a failure to reset the
error count from a previous triggered rule (the condition of failure
is much more rare than this explanation makes it sound, which is why
it went undiscovered for so long).
attached to a label in a GDS input file; the scalefactor that was
being used is reset at the beginning of a GDS read, and so becomes
invalid after a database rescaling, resulting in improperly scaled
label geometry if "gds read" is used more than once.
I understand the problem, which is that nodes are ordered according
to precedence of EFHNBest() within a circuit, but there is no
concept of ordering between circuits. So ports end up listing nodes
in arbitrary order, and the only way to resolve the order is to use
EFHNBest() as is done within a subcircuit. Appears to work for
different edge cases tested.
ports, to avoid creating ports for node names that are redundant.
It would probably be better to avoid creating the redundant node
names in the first place; however, I am less certain why these
are generated. The incorrect additional ports all have hierarchical
names in the cell, which is a sign that they are incorrect, as the
cell itself should not have any parents. The level of certainty
about this fix is definitely not 100%, but it was tested on a
hierarchical analog design, and setting levels of parasitic caps
caused new nodes to appear in subcircuits and in no cases did
information appear to be lost.
with ext2spice without the hierarchy option. More work needed to
produce correct hierarchical output and to support extraction
devices other than the old "fet" record.
it only complains about (i.e., issues an error message) ports with
the same index but different text, indicating a read port number
collision and a true error.
the below-threshold coupling caps being removed from the hierarchy,
added code to suppress the error message when it is clearly related
to a below-threshold cap that has been removed.
used with "ext2spice hierarchy on" because the device index is not
reset between calls to output cells in the hierarchy, leading to
a mismatch of the index for all cells after the first one output.
checks. Added new command "antennacheck" and a routine that
adds feedback entries where violations are found. Extended the
syntax of the extraction section of the techfile to support the
antenna ratios and antenna calculation methods.
simple FET device in extresist. Also: Extended the bloat-all CIF operator
again, allowing the trigger layer for the bloat operation to include both
CIF layers and magic layers (previously only magic layers were supported).
This extension is possible due to the previous extension allowing the
trigger layer and bloating layers to be on separate planes. This operator
extension is useful for tagging geometry that is in the proximity of, but
not overlapping, geometry on another plane.
error whenever there are no DRC-CIF rules in the techfile. The
same error will be raised anyway when reading the techfile if
DRC-CIF rules are declared without a style being specified.
Tim Edwards