determining what does and doesn't get into the R-C extraction
output. Added option "debug" and moved all excess diagnostic
information to be gated by this flag. Corrected an issue in
the standard extraction in which the substrate is always output
with zero lumped resistance, preventing it from being checked
by "extresist" for inclusion or exclusion in the .res.ext output.
Reinstated the computation of minimum resistance transistor but
excluded other devices. Added more sane handling of exceptional
conditions like loops. The result is a more consistent check of
nets in the design. However, I still need to recheck the
"rg_maxres" calculation because it appears to be too low.
(1) An incorrect use of ExtResetTiles() was found in "extresist"
which impacts performance, especially for small nets.
(2) Corrected units for resistance tolerance in extresist, and
handled output printing in fs when delay values get below ps
size.
(3) Added command option "extract do unique notopports" to be the
extraction option equivalent of the standalone command
"extract unique notopports".
(4) Changed the "extresist" default for "mindelay" to 1ps from 0,
in response to the observation that lumped resistance from
"extract" can be an extreme overestimate, and the extracted
time delay from "extesist" calculations should be used as a
better determination of whether a net should be output as a
resistor network or not.
(5) Added documentation for both "extract do unique notopports"
and the change to the "extresist" default values.
that "extresist" selects or rejects networks for resistance
extraction. The "tolerance" value, which nobody (including
myself) seems to understand, is now deprecated, replaced by
a handful of more meaningful options: "threshold" to set a
lumped resistance estimate threshold to determined whether or
not to extract a network; "minres" to specify when to prune
small resistors from the resulting tree network, and "mindelay"
to gate the selection and output on the estimated signal
propagation delay. With these settings, I am much better able
to control the size and complexity of the resulting output.
overhaul was to introduce the concept of a "connection point"
between two cells to the ".ext" file format so that it becomes
possible to do proper hierarchical R-C extraction. Previously
this information was not kept in the .ext file, making it
impossible for "extresist" to know what sub-net of a net connects
up or down the hierarchy. However, additional changes were made
to the extresist code (in the resis/ directory) to add the
handling of connections up and down the hierarchy, and to make
the code a lot clearer and fix ambiguous variable and subroutine
names.
reading the .sim file format to reading the .ext file format, which
is that .sim files use capacitance values of fF while .ext files
use capacitance values of (nominally) aF. So there was a conversion
factor of 1000 left over from the .sim file reading code that needed
to be removed, or else parasitic values come out to be 1000 times too
high.
the location of a node which was previously read as a port. But
the port location was not set when reading the port, only the
drivepoint, so the location is undefined and can cause a program
crash.
code which are relevant and need to be included. Current state
is that hierarchical extresist "basically works" but entry and
exit points through the hierarchy are not being examined, so
results are currently based on port positions and not actual
connections. Also, proper distribution of coupling caps has not
yet been worked on.
Rebased, fixing merge conflict.
"extresist" command continues to work as before. However, the
method now reads from .ext files instead of .sim files, so
generating ".sim" and ".nodes" files is no longer necessary.
In addition, the core code of "extresist" was put directly into
ExtCell.c so that full R-C extraction can be run using
"extract do resistance" followed by "extract all", without
needing to run "extresist" at all other than to set parameters
(e.g., "extresist tolerance 10").
R. Timothy Edwards