could have multiple ports of the same name. This problem had been
worked over before, but there was an indpendent mechanism producing
the same result for a completely different reason, caused by subcells
being much larger than the cookie-cutter extraction method's extraction
regions. Solved by tracking port names in a hash table and preventing
re-use. (2) ext2spice was producing "no such node" errors; like (1)
this had been previously worked on, and like (1) this mechanism was
independent. Problem came from not passing -1 to extHierSubstrate for
the non-arrayed dimension of a 1-dimensional array. Also: Removed
the word "fatal" from extraction error reporting, as nearly all
extraction errors are entirely benign. This should clear up confusion
among alarmed end-users.
unique" code. It was using DBEraseLabelsByContent() which would
erase all matching labels, and could potentially erase labels that
were still remaining on the list being processed, causing a segfault.
Also corrected minor errors identified by valgrind during debugging
the above-referenced problem.
such that it looks for material connecting to the label at the
center point of the label and not the lower left corner. This keeps
the behavior of looking for tiles on the corners of a degenerate
label line or point between layers, but avoids problems with sticky
labels that are not quite aligned with the rectangle (due to certain
commercial EDA tools that have a sloppier notion of labeling).
p device; this was previously dependent only on the first character
of the extracted device model name. Since the tech file has control
over what the device layer names are but not the extracted model
names, the device layer type name is used as a backup way to determine
if the type is n or p, if that cannot be determined from the extracted
model name.
with two or more terminals other than the device identifier type
tied together) would fail if there were not a device record
specifically matching a one-S/D-terminal device. This is
inconsistent with past behavior, and so has been fixed.
because the opposite type (pwell) is not directly underneath the
gate, but touches it on the plane below. Because the pwell may
be represented by space tiles on the well plane, it was also
necessary to deal with the space type in the bitmask.
type in the device record, which was not updated at the end of
checking terminals for matching device extraction types. so the
boundary survey might see the wrong device type and generate an
incorrect boundary survey as a result.
support asymmetric FETs and other devices like bipolars that have
three distinct terminals. This does not go as far as it should to
make the array independent of the number of declared terminals of
the device. However, it suffices to make, e.g., parameter "a2=area"
work for a bipolar device, and to generate the right drain and source
areas and perimeters for asymmetric (e.g., extended-drain) devices.
device layer type to describe the extraction for both a regular FET
and an extended-drain device. Note that the current code still
requires that the extended-drain device be declared first, and does
not check for this or attempt to reorder if incorrect.
supposed to pull "sticky labels" into the cumulative flattened
layout. Because it failed to check for the "sticky" flag, it
would copy all labels, causing extraction time to go exponential
as the number of labels in the design increases. Based on this
correction, the extHierConnectFunc1() routine should be able to
be optimized by stopping the search for sticky labels on the first
non-sticky label, since extSubtreeFunc() ensures that all sticky
labels come first in the label list.
the extractor was not checking temp_subsname as well as glob_subsname,
and so was failing to apply the substrate name to child cells in
"merge" statements in the extract file, causing the substrate to get
disconnected between parent and child.
works for the first pair of types/plane being below the second pair of
types/plane (upward fringing from the top of a wire to an overlapping
wire above it), which was not being handled due to an implicit assumption
that plane1 < plane2, which does not have to be the case.
could cause serious errors on systems that do not auto-zero allocated
memory. Also: Fixed an error introduced by a recent commit to allocate
character memory for efReadLine() which frees the memory before reading
a .res.ext file, causing a crash when using "ext2spice" with the
"extresist on" option.
optional name field to the "substrate" line in the extract section
of the techfile. This is the default name of the substrate if not
connected to anything labeled. It may use a Tcl variable (preferred).
(2) Added command option "instance orientation [-def]" that returns
the orientation of the named or selected instance. The -def option
returns the orientation using DEF naming convention; otherwise, the
naming used with "getcell" is generated.
areas and writes ANTENNAGATEAREA and ANTENNADIFFAREA values.
(2) Determines "USE POWER" or "USE GROUND" from label names
matching Tcl variables $VDD and $GND, if the USE has not been
registered as a cell property (knowning the use allows magic
to avoid writing an ANTENNADIFFAREA for power rails, although
doing so should not be an issue).
not copy labels; not copying labels speeds up the antenna checks
(which don't need labels) greatly. Also fixed several numerical
overflow problems in the antenna checks, which resulted in false
positive errors, as well as nonsensical results.
Conflicts:
VERSION
Merged recent changes from master back into bplane, as the efficiency of
bplane for doing extraction on large layouts is unquestionably better.
Fixed the implementation of DBMoveCell() for bplane. Corrected an error
in the bplane version of dbScaleCell() that enumerates cell uses but
does not free the list.
generating duplicate devices that may have parts overlaid in
different subcells; this failed to filter the check by plane of
the device, and so if any two devices exist at the same point in
two different planes (e.g., metal resistor and a transistor), one
of them would get eliminated.
Conflicts:
VERSION
calma/Depend
cif/Depend
cmwind/Depend
commands/Depend
database/Depend
dbwind/Depend
debug/Depend
drc/Depend
ext2sim/Depend
ext2spice/Depend
extflat/Depend
extract/Depend
garouter/Depend
gcr/Depend
graphics/Depend
grouter/Depend
irouter/Depend
lef/Depend
lisp/Depend
mzrouter/Depend
netmenu/Depend
plot/Depend
plow/Depend
resis/Depend
router/Depend
select/Depend
sim/Depend
tcltk/Depend
textio/Depend
tiles/Depend
utils/Depend
windows/Depend
wiring/Depend
Merged recent changes from master branch into bplane branch. Testing the
bplane implementation which has about a 5x improvement in extraction times
for large layouts, which is significant enough to move ahead with the bplane
implementation; however, the bplane implementation has not been thoroughly
vetted yet, so it will remain a branch until such time that it has been
validated.
substrate more than once for the same subcell, since the substrate
extraction method scans the entire plane area; this was making
large standard cell layouts extract very slowly, as every component
cell was causing the substrate search to be repeated.
extraction: Fixed a problem causing long extraction times, at
least some of which had to do with a poor string hash function
implementation. Fixed a huge problem in ext2spice, where the
node merge function was particularly poorly implemented, causing
exponentially increasing processing times with layout size.
Corrected a minor issue with ext2spice where arguments were
improperly specified, causing unnecessary error messages to be
issued. Fixed an error in the "load -dereference" command option,
which again caused unnecessary error messages to be issued.
Changed .gitignore to ignore Depend files, which are now regenerated
on every build.
Conflicts:
VERSION
database/DBcellsrch.c
database/DBconnect.c
extract/ExtInter.c
lef/Depend
utils/Depend
Updated bplane branch with all changes to master since the bplane branch
was last modified.
only at the time of running the command "load". But cells are generally
loaded only on an as-needed basis, so the dereferencing option must be
saved as a flag in the cell and honored whenever its subcells are expanded
or otherwise read at a later time.
include (1) specification of sidewall or surface to use for
each type individually, rather than a single method for all
types, and (2) specification of a linear model R = Ax + B for
the ratio limit when diodes are attached to the wire, where x
is the diode surface area (unitless, as this is a ratio).
like resistors where a tile other than space may border the resistor
device on its non-terminal sides (which is handled correctly, and
should not be considered an error).
rid of redundant port entries in subcircuits. There is still an outstanding
issue as to whether nodes and connections need to be recursively iterated
to the hierarchy bottom. The current fix corrected the test case. Also,
added a "-dereference" option to the "load" command to revert to the
original behavior of using only search paths from "addpath" when searching
for files to load.
to multiple entries per device; the resistor length and width calculating
routine lost a break statement and would go into an infinite loop for
resistors with bends in them.
checks. Added new command "antennacheck" and a routine that
adds feedback entries where violations are found. Extended the
syntax of the extraction section of the techfile to support the
antenna ratios and antenna calculation methods.
perimeter were not output because of recent code that broke the
routine that assigns the resistance classes to devices. This is
now fixed. Thanks to Dan Moore for bringing this to my attention,
and debugging investigations.
Tim Edwards