diff --git a/VERSION b/VERSION
index 4814dde4..8efdaa1d 100644
--- a/VERSION
+++ b/VERSION
@@ -1 +1 @@
-8.3.537
+8.3.538
diff --git a/ext2sim/ext2sim.c b/ext2sim/ext2sim.c
index ad6ece6b..f50f985f 100644
--- a/ext2sim/ext2sim.c
+++ b/ext2sim/ext2sim.c
@@ -1127,6 +1127,13 @@ simdevVisit(
 	    fprintf(esSimF, "x");
 	    break;
 
+	case DEV_VERILOGA:
+	    /* Treat verilog-A models as subcircuits (for now, anyway)	*/
+	    /* since IRSIM has no concept of verilog-A models.		*/
+	    is_subckt = TRUE;
+	    fprintf(esSimF, "x");
+	    break;
+
 	default:
 	    fprintf(esSimF, "%c", EFDevTypes[dev->dev_type][0]);
 	    break;
diff --git a/ext2spice/ext2hier.c b/ext2spice/ext2hier.c
index 94d8d8a1..093ef71d 100644
--- a/ext2spice/ext2hier.c
+++ b/ext2spice/ext2hier.c
@@ -688,6 +688,9 @@ spcdevHierVisit(
 	case DEV_CAPREV:
 	    devchar = 'C';
 	    break;
+	case DEV_VERILOGA:
+	    devchar = 'N';
+	    break;
 	case DEV_SUBCKT:
 	case DEV_RSUBCKT:
 	case DEV_CSUBCKT:
@@ -725,6 +728,7 @@ spcdevHierVisit(
 		fprintf(esSpiceF, "%d", esVoltNum++);
 		break;
 	    case DEV_SUBCKT:
+	    case DEV_VERILOGA:
 	    case DEV_RSUBCKT:
 	    case DEV_CSUBCKT:
 	    case DEV_MSUBCKT:
@@ -778,6 +782,7 @@ spcdevHierVisit(
 	    /* Drop through to below (no break statement) */
 
 	case DEV_SUBCKT:
+	case DEV_VERILOGA:
 	case DEV_CSUBCKT:
 
 	    /* Subcircuit is "Xnnn gate [source [drain [sub]]]"		*/
@@ -809,8 +814,8 @@ spcdevHierVisit(
 		    spcdevOutNode(hc->hc_hierName, source->dterm_node->efnode_name->efnn_hier,
 				"subckt", esSpiceF);
 	    }
-	    /* The following only applies to DEV_SUBCKT*, which may define as	*/
-	    /* many terminal types as it wants.					*/
+	    /* The following only applies to DEV_SUBCKT and DEV_VERILOGA, which	*/
+	    /* may define as many terminal types as they want.			*/
 
 	    for (i = 4; i < dev->dev_nterm; i++)
 	    {
diff --git a/ext2spice/ext2spice.c b/ext2spice/ext2spice.c
index fdf38e2b..a32320e5 100644
--- a/ext2spice/ext2spice.c
+++ b/ext2spice/ext2spice.c
@@ -2531,6 +2531,7 @@ spcdevVisit(
     switch(dev->dev_class)
     {
 	case DEV_SUBCKT:
+	case DEV_VERILOGA:
 	case DEV_RSUBCKT:
 	case DEV_CSUBCKT:
 	case DEV_MSUBCKT:
@@ -2624,6 +2625,9 @@ spcdevVisit(
 	case DEV_CAPREV:
 	    devchar = 'C';
 	    break;
+	case DEV_VERILOGA:
+	    devchar = 'N';
+	    break;
 	case DEV_SUBCKT:
 	case DEV_RSUBCKT:
 	case DEV_CSUBCKT:
@@ -2665,6 +2669,7 @@ spcdevVisit(
 		fprintf(esSpiceF, "%d", esVoltNum++);
 		break;
 	    case DEV_SUBCKT:
+	    case DEV_VERILOGA:
 	    case DEV_RSUBCKT:
 	    case DEV_CSUBCKT:
 	    case DEV_MSUBCKT:
@@ -2716,6 +2721,7 @@ spcdevVisit(
 
 	case DEV_SUBCKT:
 	case DEV_CSUBCKT:
+	case DEV_VERILOGA:
 
 	    /* Subcircuit is "Xnnn gate [source [drain [sub]]]"		*/
 	    /* Subcircuit .subckt record must be ordered to match!	*/
@@ -2746,8 +2752,8 @@ spcdevVisit(
 				name, esSpiceF);
 	    }
 
-	    /* The following only applies to DEV_SUBCKT*, which may define as	*/
-	    /* many terminal types as it wants.					*/
+	    /* The following only applies to DEV_SUBCKT and DEV_VERILOGA, which	*/
+	    /* may define as many terminal types as they want.			*/
 
 	    for (i = 4; i < dev->dev_nterm; i++)
 	    {
@@ -4251,6 +4257,7 @@ parallelDevs(
 	/* There is no way to merge subcircuit devices */
 
 	case DEV_SUBCKT:
+	case DEV_VERILOGA:
 	case DEV_RSUBCKT:
 	case DEV_CSUBCKT:
 	    break;
diff --git a/extflat/EFbuild.c b/extflat/EFbuild.c
index bd2508a7..a909adca 100644
--- a/extflat/EFbuild.c
+++ b/extflat/EFbuild.c
@@ -891,6 +891,7 @@ efBuildDevice(def, class, type, r, argc, argv)
 		argstart = 2;
 	    break;
 	case DEV_SUBCKT:
+	case DEV_VERILOGA:
 	case DEV_MSUBCKT:
 	case DEV_RSUBCKT:
 	case DEV_CSUBCKT:
@@ -977,6 +978,7 @@ efBuildDevice(def, class, type, r, argc, argv)
 	case DEV_CSUBCKT:
 	case DEV_MSUBCKT:
 	case DEV_SUBCKT:
+	case DEV_VERILOGA:
 	case DEV_DIODE:
 	case DEV_NDIODE:
 	case DEV_PDIODE:
diff --git a/extflat/EFread.c b/extflat/EFread.c
index 6865f6ea..446be66c 100644
--- a/extflat/EFread.c
+++ b/extflat/EFread.c
@@ -49,7 +49,8 @@ static char rcsid[] __attribute__ ((unused)) = "$Header: /usr/cvsroot/magic-8.0/
 /* This must match the definition for extDevTable in extract/ExtBasic.c */
 const char * const extDevTable[] = {"fet", "mosfet", "asymmetric", "bjt", "devres",
 		"devcap", "devcaprev", "vsource", "diode", "pdiode",
-		"ndiode", "subckt", "rsubckt", "msubckt", "csubckt", NULL};
+		"ndiode", "subckt", "rsubckt", "msubckt", "csubckt",
+		"veriloga", NULL};
 #endif
 
 /*
@@ -368,6 +369,7 @@ readfile:
 			   ac = 9;	/* Has device L and W */
 			break;
 		    case DEV_SUBCKT:
+		    case DEV_VERILOGA:
 		    case DEV_MSUBCKT:
 		    case DEV_RSUBCKT:
 		    case DEV_CSUBCKT:
diff --git a/extflat/EFvisit.c b/extflat/EFvisit.c
index 0471af8a..c7de1040 100644
--- a/extflat/EFvisit.c
+++ b/extflat/EFvisit.c
@@ -186,6 +186,7 @@ EFGetLengthAndWidth(dev, lptr, wptr)
 	case DEV_ASYMMETRIC:
 	case DEV_BJT:
 	case DEV_SUBCKT:
+	case DEV_VERILOGA:
 	case DEV_MSUBCKT:
 	case DEV_RSUBCKT:
 	case DEV_CSUBCKT:
diff --git a/extract/ExtBasic.c b/extract/ExtBasic.c
index f5f060dc..24ab6f63 100644
--- a/extract/ExtBasic.c
+++ b/extract/ExtBasic.c
@@ -57,7 +57,7 @@ static char sccsid[] = "@(#)ExtBasic.c	4.13 MAGIC (Berkeley) 12/5/85";
 #ifdef MAGIC_WRAPPER
 const char * const extDevTable[] = {"fet", "mosfet", "asymmetric", "bjt", "devres",
 	"devcap", "devcaprev", "vsource", "diode", "pdiode", "ndiode",
-	"subckt", "rsubckt", "msubckt", "csubckt", NULL};
+	"subckt", "rsubckt", "msubckt", "csubckt", "veriloga", NULL};
 #endif
 
 /* --------------------- Data local to this file ---------------------- */
@@ -2525,6 +2525,7 @@ extOutputDevices(def, transList, outFile)
 	    case DEV_MOSFET:
 	    case DEV_BJT:
 	    case DEV_SUBCKT:
+	    case DEV_VERILOGA:
 	    case DEV_MSUBCKT:
 	    case DEV_ASYMMETRIC:
 		length = 0;
diff --git a/extract/ExtTech.c b/extract/ExtTech.c
index af374abc..bdb512a6 100644
--- a/extract/ExtTech.c
+++ b/extract/ExtTech.c
@@ -197,7 +197,7 @@ static const keydesc keyTable[] = {
  * Table used for parsing the "device" keyword types
  *
  * (Note: "10" for max types in subcircuit is arbitrary---the parser
- * ignores max types for DEV_SUBCKT and DEV_MSUBCKT).
+ * ignores max types for DEV_SUBCKT, DEV_MSUBCKT, and DEV_VERILOGA).
  */
 
 /* types are enumerated in extract.h */
@@ -239,6 +239,9 @@ static const keydesc devTable[] = {
     {"csubcircuit",	DEV_CSUBCKT,		4,	7,
 "name dev-types terminal-types [sub-types|None sub-node] [options]"},
 
+    {"veriloga",	DEV_VERILOGA,		3,	11,
+"name dev-types [N] [term1-types ... termN-types [sub-types|None sub-node]] [options]"},
+
     {0}
 };
 
@@ -2544,13 +2547,14 @@ ExtTechLine(sectionName, argc, argv)
 
 	    /* Check the number of arguments after splitting out	*/
 	    /* parameter entries.  There is no limit on arguments in	*/
-	    /* DEV_SUBCKT and DEV_MSUBCKT.				*/
+	    /* DEV_SUBCKT, DEV_MSUBCKT, and DEV_VERILOGA.		*/
 
 	    class = dv->k_key;
 	    switch (class)
 	    {
 		case DEV_SUBCKT:
 		case DEV_MSUBCKT:
+		case DEV_VERILOGA:
 		    break;
 		default:
 		    /* If parameters were saved but the	*/
@@ -2698,6 +2702,7 @@ ExtTechLine(sectionName, argc, argv)
 
 		case DEV_SUBCKT:
 		case DEV_MSUBCKT:
+		case DEV_VERILOGA:
 		    // Determine if [substrate, name] optional arguments
 		    // are present by checking if the last argument
 		    // parses as a layer list.
diff --git a/extract/extract.h b/extract/extract.h
index 4d993a3d..142b22f6 100644
--- a/extract/extract.h
+++ b/extract/extract.h
@@ -55,6 +55,7 @@ extern int ExtDoWarn;		/* Bitmask of above */
 #define DEV_RSUBCKT    12		/* Resistor-like subcircuit.	*/
 #define DEV_MSUBCKT    13		/* MOSFET-like subcircuit.	*/
 #define DEV_CSUBCKT    14		/* Capacitor-like subcircuit.	*/
+#define DEV_VERILOGA   15		/* Verilog-A model ("N" component) */
 
 /* Device names for .ext file output (new in version 7.2)	*/
 /* (defined in extract/ExtBasic.c *and* extflat/EFread.c)	*/