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Two fixes: One by Claude Fable 5 which identified the two possible 

degenerate cases when attempting to find resistors in triangle
topologies in ResMerge, which fixes the segfault in github issue
diagnostic message.  The other fix is part of github issue #538,
which found an error in the check for tied transistor sources and
drains.  However, the other part of that issue, having to do with
nondeterminism in the "extresist" output, has not yet been addressed.
This commit is contained in:
R. Timothy Edwards 2026-07-08 13:25:01 -04:00
parent 07d98a33c2
commit 767cde0efc
2 changed files with 30 additions and 1 deletions
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14
resis/ResMerge.c
View File

@ -595,10 +595,24 @@ ResTriangleCheck(resptr)
if (TTMaskHasType(ResNoMergeMask + rr1->rr_tt, rr3->rr_tt))
continue;
/* rr3 must span two distinct neighbors of resptr, so */
/* skip rr3 if it is the resistor connecting resptr */
/* and n1. */
if (rr3 == rr1) continue;
/* One connection is always n1; find the other one */
n2 = rr3->rr_connection1;
if (n2 == n1) n2 = rr3->rr_connection2;
/* A resistor with both connections on n1 is a loop, */
/* pending elimination when n1 is processed, and is */
/* not a triangle side. Without this check, the hash */
/* lookup of n2 (== n1) finds n1's own table entry, */
/* the "triangle" degenerates with rr2 == rr1, and the */
/* network is corrupted, eventually causing a double */
/* free of rr1 (preceded by "Missing rptr" messages). */
if (n2 == n1) continue;
he2 = HashLookOnly(&NodeResTable, (char *)n2);
if (he2)
{

17
resis/ResRex.c
View File

@ -1155,7 +1155,7 @@ ResProcessNode(
t2 = ptr->nextDev->thisDev;
if (t1->gate != t2->gate) break;
if ((t1->source != t2->source || t1->drain != t2->drain) &&
(t1->source != t2->drain || t2->drain != t2->source))
(t1->source != t2->drain || t1->drain != t2->source))
break;
/* Sum the W/L value of devices in parallel */
@ -1912,6 +1912,21 @@ devSortFunc(rec1, rec2)
{
return 1;
}
else if ((dev1->terminal == SOURCE &&
dev2->terminal == SOURCE &&
rd1->drain == rd2->drain) ||
(dev1->terminal == SOURCE &&
dev2->terminal == DRAIN &&
rd1->drain == rd2->source) ||
(dev1->terminal == DRAIN &&
dev2->terminal == SOURCE &&
rd1->source == rd2->drain) ||
(dev1->terminal == DRAIN &&
dev2->terminal == DRAIN &&
rd1->source == rd2->source))
{
return 0;
}
}
return -1;
}