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One more correction to limit, by default, the generation of "equiv"

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statements in the .ext file output to those that mark a port as
equivalent to the node name used elsewhere in the file.  This
limits unnecessary output of "equiv" statements that can bog down
ext2spice and other commands that use the .ext file contents.
This commit is contained in:
Tim Edwards
2021-10-07 21:36:10 -04:00
parent 6b1365708d
commit 4fae7a1a2b
3 changed files with 22 additions and 6 deletions
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extract/ExtBasic.c
+18 -6
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@@ -733,19 +733,31 @@ extOutputNodes(nodeList, outFile)
for (ll = reg->nreg_labels; ll; ll = ll->ll_next)
{
bool isPort = (ll->ll_attr == LL_PORTATTR) ? TRUE : FALSE;
bool isPort;
/* Do not export aliases that are not ports unless the */
/* "extract do aliases" options was selected. */
if (!(ExtOptions & EXT_DOALIASES) && (!isPort)) continue;
if (ll->ll_label->lab_text == text)
{
isPort = (ll->ll_attr == LL_PORTATTR) ? TRUE : FALSE;
for (ll = ll->ll_next; ll; ll = ll->ll_next)
if (extLabType(ll->ll_label->lab_text, LABTYPE_NAME))
if (strcmp(text, ll->ll_label->lab_text))
{
fprintf(outFile, "equiv \"%s\" \"%s\"\n",
if ((ll->ll_attr == LL_PORTATTR) ||
(ExtOptions & EXT_DOALIASES))
{
fprintf(outFile, "equiv \"%s\" \"%s\"\n",
text, ll->ll_label->lab_text);
if (isPort && (ll->ll_attr == LL_PORTATTR))
TxError("Warning: Ports \"%s\" and \"%s\" are"
" electrically shorted.\n",
text, ll->ll_label->lab_text);
if (isPort && (ll->ll_attr == LL_PORTATTR))
TxError("Warning: Ports \"%s\" and \"%s\" are"
" electrically shorted.\n",
text, ll->ll_label->lab_text);
}
}
break;
}