Modified the LEF write routine so that it will not output ports
that have no geometry (that do not exist on planes defined in LEF).
This commit is contained in:
Tim Edwards
parent
6adb5dbacf
commit
1e9334664c
237
lef/lefWrite.c
237
lef/lefWrite.c
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@ -301,6 +301,7 @@ typedef struct
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float oscale; /* units scale conversion factor */
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int pNum; /* Plane number for tile marking */
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int numWrites; /* Track number of writes to output */
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bool needHeader; /* TRUE if PIN record header needs to be written */
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int lefMode; /* can be LEF_MODE_PORT when searching
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* connections into ports, or
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* LEF_MODE_OBSTRUCT when generating
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@ -529,6 +530,15 @@ lefWriteGeometry(tile, cdata)
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if (!TTMaskHasType(&lefdata->rmask, ttype)) return 0;
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if (lefdata->needHeader)
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{
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/* Reset the tile to not visited and return 1 to */
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/* signal that something is going to be written. */
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TiSetClient(tile, (ClientData)CLIENTDEFAULT);
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return 1;
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}
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if (lefdata->numWrites == 0)
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{
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if (lefdata->lefMode == LEF_MODE_PORT)
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@ -654,6 +664,102 @@ typedef struct _labelLinkedList {
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struct _labelLinkedList *lll_next;
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} labelLinkedList;
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/*
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* ----------------------------------------------------------------------------
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*
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* LefWritePinHeader --
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*
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* Write the PIN record for the LEF macro along with any known properties
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* such as CLASS and USE. Discover the USE POWER or GROUND if it is not
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* set as a property and the label name matches the Tcl variables $VDD
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* or $GND.
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*
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* Returns TRUE if the pin is a power pin, otherwise FALSE.
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*
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* ----------------------------------------------------------------------------
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*/
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bool
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LefWritePinHeader(f, lab)
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FILE *f;
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Label *lab;
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{
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bool ispwrrail = FALSE;
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fprintf(f, " PIN %s\n", lab->lab_text);
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if (lab->lab_flags & PORT_CLASS_MASK)
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{
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fprintf(f, " DIRECTION ");
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switch(lab->lab_flags & PORT_CLASS_MASK)
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{
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case PORT_CLASS_INPUT:
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fprintf(f, "INPUT");
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break;
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case PORT_CLASS_OUTPUT:
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fprintf(f, "OUTPUT");
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break;
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case PORT_CLASS_TRISTATE:
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fprintf(f, "OUTPUT TRISTATE");
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break;
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case PORT_CLASS_BIDIRECTIONAL:
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fprintf(f, "INOUT");
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break;
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case PORT_CLASS_FEEDTHROUGH:
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fprintf(f, "FEEDTHRU");
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break;
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}
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fprintf(f, " ;\n");
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}
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ispwrrail = FALSE;
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if (lab->lab_flags & PORT_USE_MASK)
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{
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fprintf(f, " USE ");
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switch(lab->lab_flags & PORT_USE_MASK)
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{
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case PORT_USE_SIGNAL:
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fprintf(f, "SIGNAL");
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break;
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case PORT_USE_ANALOG:
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fprintf(f, "ANALOG");
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break;
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case PORT_USE_POWER:
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fprintf(f, "POWER");
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ispwrrail = TRUE;
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break;
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case PORT_USE_GROUND:
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fprintf(f, "GROUND");
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ispwrrail = TRUE;
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break;
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case PORT_USE_CLOCK:
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fprintf(f, "CLOCK");
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break;
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}
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fprintf(f, " ;\n");
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}
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#ifdef MAGIC_WRAPPER
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else
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{
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char *pwr;
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/* Determine power rails by matching the $VDD and $GND Tcl variables */
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pwr = (char *)Tcl_GetVar(magicinterp, "VDD", TCL_GLOBAL_ONLY);
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if (pwr && (!strcmp(lab->lab_text, pwr)))
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{
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ispwrrail = TRUE;
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fprintf(f, " USE POWER ;\n");
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}
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pwr = (char *)Tcl_GetVar(magicinterp, "GND", TCL_GLOBAL_ONLY);
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if (pwr && (!strcmp(lab->lab_text, pwr)))
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{
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ispwrrail = TRUE;
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fprintf(f, " USE GROUND ;\n");
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}
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}
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#endif
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return ispwrrail;
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}
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/*
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* ----------------------------------------------------------------------------
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*
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@ -911,78 +1017,6 @@ lefWriteMacro(def, f, scale, hide)
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if (lab->lab_flags & PORT_VISITED) continue;
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fprintf(f, " PIN %s\n", lab->lab_text);
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if (lab->lab_flags & PORT_CLASS_MASK)
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{
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fprintf(f, " DIRECTION ");
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switch(lab->lab_flags & PORT_CLASS_MASK)
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{
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case PORT_CLASS_INPUT:
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fprintf(f, "INPUT");
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break;
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case PORT_CLASS_OUTPUT:
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fprintf(f, "OUTPUT");
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break;
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case PORT_CLASS_TRISTATE:
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fprintf(f, "OUTPUT TRISTATE");
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break;
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case PORT_CLASS_BIDIRECTIONAL:
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fprintf(f, "INOUT");
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break;
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case PORT_CLASS_FEEDTHROUGH:
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fprintf(f, "FEEDTHRU");
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break;
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}
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fprintf(f, " ;\n");
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}
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ispwrrail = FALSE;
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if (lab->lab_flags & PORT_USE_MASK)
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{
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fprintf(f, " USE ");
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switch(lab->lab_flags & PORT_USE_MASK)
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{
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case PORT_USE_SIGNAL:
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fprintf(f, "SIGNAL");
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break;
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case PORT_USE_ANALOG:
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fprintf(f, "ANALOG");
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break;
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case PORT_USE_POWER:
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fprintf(f, "POWER");
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ispwrrail = TRUE;
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break;
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case PORT_USE_GROUND:
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fprintf(f, "GROUND");
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ispwrrail = TRUE;
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break;
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case PORT_USE_CLOCK:
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fprintf(f, "CLOCK");
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break;
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}
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fprintf(f, " ;\n");
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}
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#ifdef MAGIC_WRAPPER
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else
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{
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char *pwr;
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/* Determine power rails by matching the $VDD and $GND Tcl variables */
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pwr = (char *)Tcl_GetVar(magicinterp, "VDD", TCL_GLOBAL_ONLY);
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if (pwr && (!strcmp(lab->lab_text, pwr)))
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{
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ispwrrail = TRUE;
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fprintf(f, " USE POWER ;\n");
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}
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pwr = (char *)Tcl_GetVar(magicinterp, "GND", TCL_GLOBAL_ONLY);
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if (pwr && (!strcmp(lab->lab_text, pwr)))
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{
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ispwrrail = TRUE;
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fprintf(f, " USE GROUND ;\n");
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}
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}
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#endif
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/* Query pin geometry for SHAPE (to be done?) */
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/* Generate port layout geometry using SimSrConnect() */
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@ -999,11 +1033,12 @@ lefWriteMacro(def, f, scale, hide)
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/* Note: Use DBIsContact() to check if the layer is a VIA. */
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/* Presently, I am treating contacts like any other layer. */
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lc.needHeader = TRUE;
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reflab = lab;
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while (lab != NULL)
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{
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int antarea;
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int antgatearea, antdiffarea;
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labr = lab->lab_rect;
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@ -1061,33 +1096,20 @@ lefWriteMacro(def, f, scale, hide)
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// For diffusion, use the types declared in the "tiedown"
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// statement in the extract section of the techfile.
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if (ispwrrail == FALSE)
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antgatearea = 0;
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for (pNum = PL_TECHDEPBASE; pNum < DBNumPlanes; pNum++)
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{
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antarea = 0;
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for (pNum = PL_TECHDEPBASE; pNum < DBNumPlanes; pNum++)
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{
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DBSrPaintArea((Tile *)NULL, SelectDef->cd_planes[pNum],
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DBSrPaintArea((Tile *)NULL, SelectDef->cd_planes[pNum],
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&TiPlaneRect, &gatetypemask,
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lefAccumulateArea, (ClientData) &antarea);
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}
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if (antarea > 0)
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{
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fprintf(f, " ANTENNAGATEAREA %.4f ;\n",
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lc.oscale * lc.oscale * (float)antarea);
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}
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lefAccumulateArea, (ClientData) &antgatearea);
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}
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antarea = 0;
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for (pNum = PL_TECHDEPBASE; pNum < DBNumPlanes; pNum++)
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{
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DBSrPaintArea((Tile *)NULL, SelectDef->cd_planes[pNum],
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antdiffarea = 0;
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for (pNum = PL_TECHDEPBASE; pNum < DBNumPlanes; pNum++)
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{
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DBSrPaintArea((Tile *)NULL, SelectDef->cd_planes[pNum],
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&TiPlaneRect, &difftypemask,
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lefAccumulateArea, (ClientData) &antarea);
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}
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if (antarea > 0)
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{
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fprintf(f, " ANTENNADIFFAREA %.4f ;\n",
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lc.oscale * lc.oscale * (float)antarea);
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}
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lefAccumulateArea, (ClientData) &antdiffarea);
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}
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// For all geometry in the selection, write LEF records,
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@ -1103,9 +1125,25 @@ lefWriteMacro(def, f, scale, hide)
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&TiPlaneRect, &DBAllButSpaceAndDRCBits,
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lefYankGeometry, (ClientData) &lc);
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DBSrPaintArea((Tile *)NULL, lc.lefYank->cd_planes[pNum],
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while (DBSrPaintArea((Tile *)NULL, lc.lefYank->cd_planes[pNum],
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&TiPlaneRect, &lc.rmask,
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lefWriteGeometry, (ClientData) &lc);
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lefWriteGeometry, (ClientData) &lc) == 1)
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{
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/* needHeader was set and there was something to write, */
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/* so write the headr and then re-run the search. */
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ispwrrail = LefWritePinHeader(f, lab);
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if (ispwrrail == FALSE)
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{
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if (antgatearea > 0)
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fprintf(f, " ANTENNAGATEAREA %.4f ;\n",
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lc.oscale * lc.oscale * (float)antgatearea);
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if (antdiffarea > 0)
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fprintf(f, " ANTENNADIFFAREA %.4f ;\n",
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lc.oscale * lc.oscale * (float)antdiffarea);
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}
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lc.needHeader = FALSE;
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}
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DBSrPaintArea((Tile *)NULL, SelectDef->cd_planes[pNum],
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&TiPlaneRect, &DBAllButSpaceAndDRCBits,
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@ -1128,7 +1166,8 @@ lefWriteMacro(def, f, scale, hide)
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}
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LEFtext = MakeLegalLEFSyntax(reflab->lab_text);
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fprintf(f, " END %s\n", reflab->lab_text); /* end of pin */
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if (lc.needHeader == FALSE)
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fprintf(f, " END %s\n", reflab->lab_text); /* end of pin */
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if (LEFtext != reflab->lab_text) freeMagic(LEFtext);
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if (maxport >= 0)
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