Updated Deep Verification Base (markdown)

Matthias Köfferlein 2018-12-31 00:51:58 +01:00
parent 0de6f8c111
commit 1acce7b21d
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The Deep Verification Base development happens in the "dvb" branch: https://github.com/klayoutmatthias/klayout/tree/dvb
See more about the progress here: [DVB Log](DVB-Log)
See more about the progress here: [[DVB Log|DVB-Log]]
# The problem
@ -9,7 +9,8 @@ Verification is a fundamental task in the chip design process. KLayout basically
Two important verification methods are addressed here:
* Design rule check (DRC)
* Schematic extraction plus schematic compare. Both steps form layout vs. schematic verification (LVS)
* Schematic extraction plus schematic compare.
* Compare: both steps form layout vs. schematic verification (LVS) once a netlist compare feature is added.
KLayout supports DRC verification to some extent: