From 1acce7b21d7f317da5b24901099f4316baee58c7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Matthias=20K=C3=B6fferlein?= Date: Mon, 31 Dec 2018 00:51:58 +0100 Subject: [PATCH] Updated Deep Verification Base (markdown) --- Deep-Verification-Base.md | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/Deep-Verification-Base.md b/Deep-Verification-Base.md index 0ab1c14..a9c03ff 100644 --- a/Deep-Verification-Base.md +++ b/Deep-Verification-Base.md @@ -1,6 +1,6 @@ The Deep Verification Base development happens in the "dvb" branch: https://github.com/klayoutmatthias/klayout/tree/dvb -See more about the progress here: [DVB Log](DVB-Log) +See more about the progress here: [[DVB Log|DVB-Log]] # The problem @@ -9,7 +9,8 @@ Verification is a fundamental task in the chip design process. KLayout basically Two important verification methods are addressed here: * Design rule check (DRC) - * Schematic extraction plus schematic compare. Both steps form layout vs. schematic verification (LVS) + * Schematic extraction plus schematic compare. + * Compare: both steps form layout vs. schematic verification (LVS) once a netlist compare feature is added. KLayout supports DRC verification to some extent: