luke
/
klayout
mirror of https://github.com/KLayout/klayout.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
4,101 Commits 89 Branches 97 Tags 457 MiB
Commit Graph

1355 Commits

Author SHA1 Message Date
Matthias Koefferlein ecc83aa579 Solved #879: PCellDeclaration now knows the layout and layout knows the library 2021-11-14 17:45:52 +01:00
Matthias Koefferlein 0ca82001ed #935 fixed (checking for valid cell index) 2021-11-13 01:03:54 +01:00
Matthias Koefferlein 719eb0bce8 Fixed a potential crash on application exit 2021-11-13 00:48:27 +01:00
Matthias Koefferlein d2478881b5 Bugfix: threading issue - multiple threads accessed the same object 2021-11-10 22:30:32 +01:00
Matthias Koefferlein 379a22c86a Restored performance of some checks 2021-11-09 21:55:55 +01:00
Matthias Koefferlein 319efc1f95 Bugfix: negative output wasn't working properly for enclosing and overlap. 2021-11-09 00:32:07 +01:00
Matthias Koefferlein 4a44329e38 Enabling 'enclosed' as a (sometimes) more efficient way of implementing an enclosing check. 2021-11-08 23:18:01 +01:00
Matthias Koefferlein 9fa82f01d8 WIP (code reduction and performance enhancement of basic DRC checks) 2021-11-07 21:46:18 +01:00
Matthias Koefferlein a0367c1530 More specific clip variants after bounding boxes have been reduced in RecursiveShapeIterator 2021-11-01 17:27:52 +01:00
Matthias Koefferlein bc54ba3b99 Merge branch 'performance' into head 2021-11-01 14:32:31 +01:00
Matthias Koefferlein d244d5aac6 Debugging plus enhancments 
Basic change: DeepShapeStore+CellMapping uses (new) hier_generation_id of Layout to figure out
if the hierarchy has changed and the cache needs update.
 2021-11-01 13:49:00 +01:00
Matthias Koefferlein 64a6b3acdc WIP 2021-11-01 09:53:51 +01:00
Matthias Koefferlein 902375cc4d WIP: trying to reduce the number of DSS-internal cell mappings by caching cell maps 2021-10-31 00:59:42 +02:00
Matthias Koefferlein 455c40ced6 More consistent verbosity levels for cell mapping 2021-10-30 21:31:05 +02:00
Matthias Koefferlein ebe38912a6 Tests and documentation for dbTrans#is_complex? 2021-10-27 23:36:58 +02:00
Matthias Koefferlein 20f3733c58 WIP: lean recursive shape touch check 2021-10-27 00:38:12 +02:00
Matthias Koefferlein 596080669d WIP 2021-10-26 23:10:29 +02:00
Matthias Koefferlein 7881c0953c WIP 2021-10-24 20:28:15 +02:00
Matthias Koefferlein c6bd856331 WIP 2021-10-24 00:05:50 +02:00
Matthias Koefferlein 09df614d8a Bugfix: array iterator must not iterate on empty search box. 2021-10-22 23:52:35 +02:00
Matthias Koefferlein abe40ae99f Bugfix plus more tests 2021-10-19 20:48:13 +02:00
Matthias Koefferlein 451f57bb25 Fixed #909 (Crash on DRC) 2021-09-21 23:37:57 +02:00
Matthias Köfferlein 80fd5b79be
Merge pull request #908 from KLayout/netlist-compare-performance2 
Improving netist compare performance for array case + some enhancements
 2021-09-21 22:43:37 +02:00
Matthias Köfferlein f1e59a7dc6
Merge pull request #907 from KLayout/issue-905 
Fixed #905 (Crash while deleting a Library)
 2021-09-21 22:43:22 +02:00
Matthias Koefferlein ceb0b2298f Some cleanup, updated tests 2021-09-19 19:05:09 +02:00
Matthias Koefferlein b7827f7b5f Maybe found a solution for the matrix arrangement runtime problem 2021-09-19 18:29:57 +02:00
Matthias Koefferlein 930423bcc7 WIP 2021-09-19 17:26:28 +02:00
Matthias Koefferlein a42d761e95 Some small refactoring 2021-09-17 22:46:56 +02:00
Matthias Koefferlein 71b5695344 Fixed #905 2021-09-15 00:09:56 +02:00
Matthias Koefferlein 0f4b0e4826 Ported some enhancements from WIP branch (debug output, capturing easy wins when max depth is exhausted) 2021-09-14 22:31:24 +02:00
Matthias Koefferlein b671b1843b Fixed a problem with net compare config - depth first wasn't considered in all cases 2021-09-12 22:35:08 +02:00
Matthias Koefferlein 89052660ee Refactoring of the netlist compare code 2021-09-12 22:35:03 +02:00
Matthias Koefferlein 822709dd5a Refactoring of the netlist compare code 2021-09-12 22:34:59 +02:00
Matthias Koefferlein 52c79feeed Refactoring of the netlist compare code 2021-09-12 22:34:55 +02:00
Matthias Koefferlein ab3bceda75 Fixed #898 (netlist reader ignores last list) 2021-08-29 21:12:04 +02:00
Matthias Köfferlein 225d3ab32d
issue-892 (#895) 2021-08-24 21:37:02 +02:00
Matthias Köfferlein 1916a4f683
Merge pull request #884 from KLayout/issue-881 
Fixed #881 (typo in separation check and others)
 2021-07-31 11:01:55 +02:00
Matthias Koefferlein d7438b43ae Fixed #881 (typo in separation check and others) 2021-07-30 23:13:24 +02:00
Matthias Koefferlein 9543cea952 Fixed tests 2021-07-29 22:24:22 +02:00
Matthias Koefferlein 8b970039c0 Using primary(layout) netlist as reference for primary parameters and compare delegate - this also removes some potential glitches 2021-07-29 01:15:35 +02:00
Matthias Koefferlein a90e14b692 Some tests added. 2021-07-27 23:08:34 +02:00
Matthias Koefferlein 42b7290fe5 Device parameter comparer now also compares other (primary) parameters, parameters primary in both netlists are considered to be compared by default, 'ignore' feature in tolerance 2021-07-27 22:15:59 +02:00
Matthias Koefferlein 37457aa02f Spice reader flags existing parameters as primary 2021-07-27 22:13:45 +02:00
Matthias Koefferlein 7a37a6b7ed Implemented extent(cell_filter) for DRC, added Layout#cells with name filter 2021-07-21 18:31:51 +02:00
Matthias Koefferlein 722b45b721 Fixed tests 2021-07-19 07:47:41 +02:00
Matthias Koefferlein bc74f189f8 Introducing asymmetric ambiguity groups for better matching of black box circuits with optional pins. 2021-07-18 23:33:01 +02:00
Matthias Koefferlein 70f4c7e2b5 A small refactoring. 2021-07-18 23:09:51 +02:00
Matthias Koefferlein 2c8d065eb3 Some enhancments + test update 
1. Be more careful with net names
Net names are used now for sorting the graph nodes, but not for
strict compare. This is useful to derive swappable pins for
blackbox circuits.

2. Be more careful with pins from schematic netlist
Pins from schematic netlist without a corresponding pin on the layer
side are treated as mandatory unless connected to a trivial net.
Pins connecting to non-trivial nets inside the subcircuit are always
considered mandatory.
This way schematic pins enforce corresponding layout pins.
On the other hand, layout pins connecting to trivial nets inside
the subcircuit are considered non-mandatory.
 2021-07-18 22:34:02 +02:00
Matthias Koefferlein 51d117e379 Refined black box pin heuristics 
Pins are required to match if they are passive inside the
subcircuit but connected to a non-trivial net in the calling circuit.
 2021-07-18 20:39:19 +02:00
Matthias Koefferlein 05386668b4 Re-introducing pin name mapping for net assignment 2021-07-18 20:20:23 +02:00