General topic: abstracts and swappable pins.
Issue: we work bottom up and assign pins. This is the
basis for net graph building. But swappable means those
pins can change. The compare works fine, but debugging
output is strange: as the pin assigned is fixed, the nets
found to be attached to a circuit might not fit any
proposed pin pair (which does not contain swapping).
The problem gets worse with abstracts.
The enhancements are
- Such cases generate only warnings in the browser
and the message says swapping might be the case
- Floating nets are treated differently. This should
lead to a better performance for abstracts/black boxes,
but in case of disconnected pins (due to wire errors),
floating nets happen to create mismatches in the nets above.
- Net graph building does not consider swappable nets. In
case of two swappable pins this wouldn't be an issue, but
for more than two this would create ambiguities and
prevent topological matching.
Plus: Debug output option for net graph
Tests updated
- For unattached subcircuit pins no error should be reported
- For abstract nets, graph propagation through subcircuit pins isn't attempted.
Abstract nets are only dummy-associated currently.
Previous: empty layers occupied a special layer in the DSS
But what when empty layers are required as outputs?
ONE layer isn't good -> would overwrite the layer and it's
no longer empty for others.
So we need to keep the layers separate.
In addition, this fix includes Python-related fixes: because
of the short lifetime of Python references, the functionality
was not as expected sometimes. Keeping copies of LayerPropertiesIterators
helped. Some tweaks were required to maintain the delete() semantics.
- some refactoring
- better performance (was slow because layer iteration
was done outside of loop and recursive cluster iterator)
- with selected nets, only the required hierarchy is
produced. For this a new argument is added to
LayoutToNetlist::create_cell_mapping (nets) which
allows selecting the nets for which a cell mapping
is requested
- Two new device extractors for resistors and caps
(two-terminal only)
- R and C device classes have A and P parameters now
- A generic concept to supply terminal output layers
for device extractors (tX).
- Converted offset to transformation for devices:
this was required to make circuit flattening preserve
the geometry (transformation of devices)
L2N/LVSDB formats have been extended for this.