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281 Commits

Author SHA1 Message Date
Matthias Koefferlein d20e4b2128 Bug fixes, adjusted test data 2023-02-22 15:54:28 +01:00
Matthias Koefferlein be5e16c125 WIP: bug fixing, new test cases 2023-02-22 13:11:30 +01:00
Matthias Koefferlein 69a2ac107b One bug fix, made tests more robust and compatible with MSVC 2023-01-22 16:17:13 +01:00
Matthias Koefferlein f924109bcd WIP: implemented some TODOs 2023-01-21 16:35:01 +01:00
Matthias Koefferlein 1a9edbf6a9 WIP: refactoring - allow properties constraints modes which do not copy properties. In DRC that is default. 2023-01-21 15:13:39 +01:00
Matthias Koefferlein 045585b345 WIP: update golden test data 2023-01-21 14:08:26 +01:00
Matthias Koefferlein 7ba3133afc WIP: using net name/circuit name instead of net ID for property value as this is more stable for better regression testing. 
Bug fix: re-enabling of trace all nets tests, establishing dummy
names for layers in all cases - otherwise layers do not have a
reference for LayoutToNetlist persistence.
 2023-01-20 01:16:30 +01:00
Matthias Koefferlein 220c1b714a WIP: support for 'flatten' with properties 2023-01-19 22:20:07 +01:00
Matthias Koefferlein 984c001f56 WIP: debugging and unit test for net-aware booleans 2023-01-19 21:15:41 +01:00
Matthias Koefferlein 4edf4ab1f7 WIP: Added support for size with properties 2023-01-18 16:22:36 +01:00
Matthias Koefferlein 71d2d9ef3f WIP: tests for complex DRC ops with properties 2023-01-18 15:46:09 +01:00
Matthias Koefferlein 9f6f0e2d43 [BUGFIX] WIP: property support for DRC functions, bugfix: DRC check against raw (non-merged semantics) second input did not work 2023-01-18 12:34:47 +01:00
Matthias Koefferlein 40267dddb6 WIP: polygons to edges with properties 2023-01-17 19:07:32 +01:00
Matthias Koefferlein 5ff187a56d WIP: fixed unit tests 2023-01-17 12:37:12 +01:00
Matthias Koefferlein dfac3b1b44 WIP: Implemented property support for two-boolean 2023-01-17 11:24:08 +01:00
Matthias Koefferlein 72bb6d4a26 WIP: bug fix for deep region merge property computation - was missing on root connector clusters 2023-01-17 10:21:28 +01:00
Matthias Koefferlein 35fb4ce3db Updated testdata 2023-01-16 16:58:41 +01:00
Matthias Koefferlein 3b4a460581 WIP: Further test updates 2023-01-16 02:29:03 +01:00
Matthias Koefferlein 48b55f142a WIP: flat region tests, partially working 2023-01-16 02:06:21 +01:00
Matthias Koefferlein db870614ab [CONSIDER MERGING] grid check markers are not exactly aligned with vertexes in deep mode 2023-01-16 01:35:08 +01:00
Matthias Koefferlein 765c22e55b WIP: added missing files 2023-01-16 01:01:57 +01:00
Matthias Koefferlein 13874986b2 Bugfix, tests updated 2022-11-28 23:40:11 +01:00
Matthias Koefferlein f6f4dbeb67 Edges#in/in_and_out: tests added 2022-11-27 15:31:25 +01:00
Matthias Koefferlein 0304930136 WIP: introducing Region#in_and_out and Edges#in_and_out, support for hierachical Edges#in, Tests updated 2022-11-27 14:53:30 +01:00
Matthias Koefferlein 25e61205d2 Deep implementation of in/not_in 2022-11-27 10:37:43 +01:00
Matthias Koefferlein 9008464268 WIP: hierarchical mode for Region#in and Region#not_in 2022-11-27 10:26:01 +01:00
Matthias Koefferlein 90df9451b6 WIP: reworked log enabling in LVS, added 'no_lvs_hints' feature, updated tests 2022-08-13 18:30:02 +02:00
Matthias Koefferlein 38d2b8378d Merge remote-tracking branch 'origin/master' into wip 2022-08-10 20:40:27 +02:00
Matthias Köfferlein 7ffdc211e5
Fixed issue-1135 (LVS mismatch on parallel devices) (#1136) 
* Fixed issue-1135 (LVS mismatch on parallel devices)

The fix consists of a more elaborate device identity analysis
following the topological matching. In this step, the devices
are identified according to their connections and parameters.
It is important to properly identify devices taking their
parameters into account as well as their connections.

* Second part of issue fixed (inverter chain ambiguity)

* Added test

* Updated tests

* Updated golden test results

* Updated golden test data for Windows

Co-authored-by: klayoutmatthias <matthias@klayout.org>
 2022-08-10 20:27:11 +02:00
Matthias Koefferlein 0083021220 [Consider merging] Some refactoring of L2N and LVSDB readers for more future compatibility 2022-08-07 00:24:05 +02:00
Matthias Köfferlein 716369de63
Issue 1126 (#1128) 
* First attempt to fix. Rather experimental.

* Debugging and bug fixing

The basic issue was a missing break
However, correct computation of cache results for instance-to-instance cluster
interaction is implemented
Plus: identical and overlapping instances are no longer ignored except in the
case of exact duplicates. Otherwise these instance generate dead nets which
are not connected elsewhere.

* Added tests, fixed duplicate cells test, added missing files.

* Code simplification (removed invariant from transformation in cluster-to-cluster interaction cache)

* Skipping cell instance duplicates as some real-world testcases mandate so

* Updated test data
 2022-08-01 18:50:07 +02:00
Matthias Köfferlein 4a06bc1bb5
Another change related to issue-1011 (aligning flat and deep mode text representation for LVS) (#1037) 2022-03-16 23:33:08 +01:00
Matthias Koefferlein 834dfa6614 Bug fixes, enhancements, tests for snap and scale improvements. 2022-02-18 14:22:16 +01:00
Matthias Koefferlein 812e26aff9 Added missing file 2021-12-26 11:14:40 +01:00
Matthias Koefferlein e1cd6aaeb1 Bugfix for #954 
The bug was that while iterating a Region during the gate traversal,
the "select_interacting" was triggering a sort() which changed the
order.

Solution is to pre-sort when iterators are issued also when the
iterator is non-region selecting. This way, plain and region query
iterators can be used together. In addition, the dirty flag scheme
of Cell+Shapes was cleaned up a little for bboxes.
 2021-12-26 01:12:36 +01:00
Matthias Koefferlein a0367c1530 More specific clip variants after bounding boxes have been reduced in RecursiveShapeIterator 2021-11-01 17:27:52 +01:00
Matthias Koefferlein abe40ae99f Bugfix plus more tests 2021-10-19 20:48:13 +02:00
Matthias Koefferlein 411869d255 Added missing test file 2021-08-29 21:14:08 +02:00
Matthias Koefferlein 2b447854f9 Enhanced matching of blackbox/pin ambiguities 
Previously: matching of blackbox pins was enforced
by using pin names for passive nets in the compare.
Problem: no match was achieved when pins are not
named or not named consistently.

In this case, it's desirable to treat them as
ambiguous.

The new solution is to let the ambiguity resolver handle
that using an extended definition of the net names:
it will take the pin name into account if an unnamed net
is attached to a pin.

In addition, net ambiguities are projected to pin
equivalence now. This also will propagate symmetry
through nested blocks (dbNetlistCompareTests:20_BusLikeConnections).
 2021-07-08 23:54:20 +02:00
Matthias Koefferlein 4e0d8d92ef Updated doc, reverted netlist writer to write all parameters - it will only write primary parameters for R, L and C 2021-07-05 22:45:40 +02:00
Matthias Koefferlein 24c34f1d60 Updated test data 2021-07-05 22:29:33 +02:00
Matthias Koefferlein 79c552b300 Fixed #858 (+ line continuation after blanks in Spice reader) 2021-07-02 23:31:54 +02:00
Matthias Koefferlein 19b28982e7 WIP: updated test data (bugfix: bulk does not have layer properties), Fixed Region::count and Region::hier_count (was counting non-polygons too) 2021-05-25 23:08:38 +02:00
Matthias Koefferlein ff033893e0 Added missing file. 2021-05-13 21:13:54 +02:00
Matthias Koefferlein aea8c4d1ad 3-terminal C's and R's for Spice writer too, using different default models for 2- and 3-terminal R and C 2021-05-13 21:13:41 +02:00
Matthias Koefferlein 2f204eaa21 Some refactoring of the instance-to-instance test in hier processor: gives some performance improvement with less memory for cache. 2021-04-26 23:15:27 +02:00
Matthias Koefferlein 9b7879b2a9 Faster hierarchical edges. 2021-04-06 21:05:02 +02:00
Matthias Koefferlein 94556c1448 Merge branch 'master' into lvs-enhancements 2021-03-30 18:56:27 +02:00
Matthias Koefferlein 3f37b0e5a4 Fill cell box introduced as a concept, added tests, overlapping fill cells supported. 2021-03-29 22:12:47 +02:00
Matthias Koefferlein 8fda92a9c4 Merge branch 'drc-enhancements' into fill-enhancements 2021-03-29 15:07:47 +02:00