diff --git a/src/lvs/unit_tests/lvsSimpleTests.cc b/src/lvs/unit_tests/lvsSimpleTests.cc
index 44ee2133e..01283fa1e 100644
--- a/src/lvs/unit_tests/lvsSimpleTests.cc
+++ b/src/lvs/unit_tests/lvsSimpleTests.cc
@@ -182,7 +182,13 @@ TEST(20_double_height2_inv)
   run_test (_this, "double_height2", "double_height2_inv.gds");
 }
 
-TEST(21_split_gate)
+//  testing cell specific net joining for VSS of the double-height inverter standard cell
+TEST(21_double_height2_inv_texts)
+{
+  run_test (_this, "double_height2_texts", "double_height2_inv.gds");
+}
+
+TEST(22_split_gate)
 {
   run_test (_this, "nand2_split_gate", "nand2_split_gate.oas");
 }
diff --git a/testdata/lvs/double_height2_texts.cir b/testdata/lvs/double_height2_texts.cir
new file mode 100644
index 000000000..882e59444
--- /dev/null
+++ b/testdata/lvs/double_height2_texts.cir
@@ -0,0 +1,17 @@
+* Extracted by KLayout
+
+.SUBCKT INVCHAIN ANY R ANY$1 PWR GND
+X$1 ANY R R ANY$1 PWR GND INV2
+.ENDS INVCHAIN
+
+.SUBCKT INV2 A1 A2 Q1 Q2 R VSS
+X$1 VSS R A1 Q1 INV
+X$2 VSS R A2 Q2 INV
+.ENDS INV2
+
+.SUBCKT INV \$1 \$2 \$3 \$4
+M$1 \$4 \$3 \$2 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
++ PD=3.45U
+M$2 \$4 \$3 \$1 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
++ PD=3.45U
+.ENDS INV
diff --git a/testdata/lvs/double_height2_texts.lvs b/testdata/lvs/double_height2_texts.lvs
new file mode 100644
index 000000000..34eca592b
--- /dev/null
+++ b/testdata/lvs/double_height2_texts.lvs
@@ -0,0 +1,135 @@
+
+source($lvs_test_source)
+
+report_lvs($lvs_test_target_lvsdb)
+
+writer = write_spice(true, false)
+target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
+
+# needs this delegate because we use MOS3 which is not available in Spice
+class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
+
+  # says we want to catch these subcircuits as devices
+  def wants_subcircuit(name)
+    name == "HVNMOS" || name == "HVPMOS"
+  end
+
+  # translate the element
+  def element(circuit, el, name, model, value, nets, params)
+
+    if el != "M"
+      # all other elements are left to the standard implementation
+      return super
+    end
+
+    if nets.size != 4
+      error("Device #{model} needs four nodes")
+    end
+
+    # provide a device class
+    cls = circuit.netlist.device_class_by_name(model)
+    if ! cls
+      cls = RBA::DeviceClassMOS3Transistor::new
+      cls.name = model
+      circuit.netlist.add(cls)
+    end
+
+    # create a device
+    device = circuit.create_device(cls, name)
+
+    # and configure the device
+    [ "S", "G", "D" ].each_with_index do |t,index|
+      device.connect_terminal(t, nets[index])
+    end
+    device.set_parameter("W", params["W"] * 1e6)
+    device.set_parameter("L", params["L"] * 1e6)
+
+    device
+
+  end
+
+end
+
+reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
+schematic("double_height_inv.cir", reader)
+
+deep
+
+# Drawing layers
+
+nwell       = input(1, 0)
+active      = input(2, 0)
+poly        = input(3, 0)
+poly_lbl    = labels(3, 1)
+diff_cont   = input(4, 0)
+poly_cont   = input(5, 0)
+metal1      = input(6, 0)
+metal1_lbl  = labels(6, 1)
+via1        = input(7, 0)
+metal2      = input(8, 0)
+metal2_lbl  = labels(8, 1)
+
+# Bulk layer for terminal provisioning
+
+bulk        = polygon_layer
+
+psd = nil
+nsd = nil
+
+# Computed layers
+
+active_in_nwell       = active & nwell
+pactive               = active_in_nwell 
+pgate                 = pactive & poly
+psd                   = pactive - pgate
+
+active_outside_nwell  = active - nwell
+nactive               = active_outside_nwell 
+ngate                 = nactive & poly
+nsd                   = nactive - ngate
+
+# Device extraction
+
+# PMOS transistor device extraction
+extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate, 
+                                "tS" => psd, "tD" => psd, "tG" => poly })
+
+# NMOS transistor device extraction
+extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate, 
+                                "tS" => nsd, "tD" => nsd, "tG" => poly })
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(psd,        diff_cont)
+connect(nsd,        diff_cont)
+connect(poly,       poly_cont)
+connect(diff_cont,  metal1)
+connect(poly_cont,  metal1)
+connect(metal1,     via1)
+connect(via1,       metal2)
+
+# attach labels
+connect(poly,       poly_lbl)
+connect(metal1,     metal1_lbl)
+connect(metal2,     metal2_lbl)
+
+# Global
+connect_global(bulk, "SUBSTRATE")
+
+# Implicit connection of the INV2
+# VSS nets
+connect_implicit("GND")
+connect_implicit("?")  # "R"
+connect_implicit("DOESNOTEXIST")
+connect_implicit("*2", "*SS")
+connect_implicit("*", "R")
+connect_implicit("DOESNOTEXIST", "DOESNOTEXIST")
+
+# Compare section
+
+netlist.simplify
+align
+
+compare
+
diff --git a/testdata/lvs/double_height2_texts.lvsdb b/testdata/lvs/double_height2_texts.lvsdb
new file mode 100644
index 000000000..b40026de2
--- /dev/null
+++ b/testdata/lvs/double_height2_texts.lvsdb
@@ -0,0 +1,325 @@
+#%lvsdb-klayout
+J(
+ W(INVCHAIN)
+ U(0.001)
+ L(l3 '3/0')
+ L(l11 '3/1')
+ L(l6 '4/0')
+ L(l7 '2/0')
+ L(l8 '6/0')
+ L(l12 '6/1')
+ L(l9 '7/0')
+ L(l10 '8/0')
+ L(l13 '8/1')
+ L(l14)
+ L(l2)
+ L(l5)
+ C(l3 l3 l11 l7)
+ C(l11 l3)
+ C(l6 l6 l8 l2 l5)
+ C(l7 l3 l7 l8)
+ C(l8 l6 l7 l8 l12 l9)
+ C(l12 l8)
+ C(l9 l8 l9 l10)
+ C(l10 l9 l10 l13)
+ C(l13 l10)
+ C(l14 l14)
+ C(l2 l6 l2)
+ C(l5 l6 l5)
+ G(l14 SUBSTRATE)
+ K(PMOS MOS3)
+ K(NMOS MOS3)
+ D(D$PMOS PMOS
+  T(S
+   R(l2 (-900 -475) (775 950))
+  )
+  T(G
+   R(l3 (-125 -475) (250 950))
+  )
+  T(D
+   R(l2 (125 -475) (775 950))
+  )
+ )
+ D(D$NMOS NMOS
+  T(S
+   R(l5 (-900 -475) (775 950))
+  )
+  T(G
+   R(l3 (-125 -475) (250 950))
+  )
+  T(D
+   R(l5 (125 -475) (775 950))
+  )
+ )
+ X(INV
+  R((-1500 -800) (3000 4600))
+  N(1
+   R(l6 (290 -310) (220 220))
+   R(l6 (-220 180) (220 220))
+   R(l8 (-290 -690) (360 760))
+   R(l9 (-305 -705) (250 250))
+   R(l9 (-250 150) (250 250))
+   R(l10 (-2025 -775) (3000 900))
+   R(l5 (-1375 -925) (775 950))
+  )
+  N(2
+   R(l6 (290 2490) (220 220))
+   R(l6 (-220 180) (220 220))
+   R(l8 (-290 -690) (360 760))
+   R(l9 (-305 -705) (250 250))
+   R(l9 (-250 150) (250 250))
+   R(l10 (-2025 -775) (3000 900))
+   R(l2 (-1375 -925) (775 950))
+  )
+  N(3
+   R(l3 (-125 -250) (250 2500))
+   R(l3 (-250 -3050) (250 1600))
+   R(l3 (-250 1200) (250 1600))
+  )
+  N(4
+   R(l6 (-510 -310) (220 220))
+   R(l6 (-220 180) (220 220))
+   R(l6 (-220 2180) (220 220))
+   R(l6 (-220 180) (220 220))
+   R(l8 (-290 -3530) (360 2840))
+   R(l8 (-360 -2800) (360 760))
+   R(l8 (-360 2040) (360 760))
+   R(l2 (-680 -855) (775 950))
+   R(l5 (-775 -3750) (775 950))
+  )
+  P(1)
+  P(2)
+  P(3)
+  P(4)
+  D(1 D$PMOS
+   Y(0 2800)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.73625)
+   E(AD 0.73625)
+   E(PS 3.45)
+   E(PD 3.45)
+   T(S 4)
+   T(G 3)
+   T(D 2)
+  )
+  D(2 D$NMOS
+   Y(0 0)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.73625)
+   E(AD 0.73625)
+   E(PS 3.45)
+   E(PD 3.45)
+   T(S 4)
+   T(G 3)
+   T(D 1)
+  )
+ )
+ X(INV2
+  R((0 0) (3000 9200))
+  N(1 I(A1)
+   J(l11 A1 (1480 7110))
+  )
+  N(2 I(A2)
+   J(l11 A2 (1520 1950))
+  )
+  N(3 I(Q1)
+   J(l12 Q1 (1920 7070))
+  )
+  N(4 I(Q2)
+   J(l12 Q2 (1940 1950))
+  )
+  N(5 I(R)
+   J(l13 R (2720 5560))
+   J(l13 R (-90 -1940))
+  )
+  N(6 I(VSS)
+   J(l13 VSS (2680 8390))
+   J(l13 VSS (-30 -7640))
+  )
+  P(1 I(A1))
+  P(2 I(A2))
+  P(3 I(Q1))
+  P(4 I(Q2))
+  P(5 I(R))
+  P(6 I(VSS))
+  X(1 INV O(180) Y(1500 8400)
+   P(0 6)
+   P(1 5)
+   P(2 1)
+   P(3 3)
+  )
+  X(2 INV M O(180) Y(1500 800)
+   P(0 6)
+   P(1 5)
+   P(2 2)
+   P(3 4)
+  )
+ )
+ X(INVCHAIN
+  R((-90 0) (3090 9200))
+  N(1 I(ANY)
+   R(l3 (-90 6850) (1590 650))
+   J(l11 ANY (-700 -350))
+  )
+  N(2 I(R)
+   J(l11 R (1480 2370))
+   R(l8 (440 4580) (690 510))
+   J(l12 R (-300 -290))
+  )
+  N(3 I(ANY)
+   R(l8 (-90 1720) (1890 470))
+   J(l12 ANY (-1170 -230))
+  )
+  N(4 I(PWR)
+   J(l13 PWR (300 5550))
+   J(l13 PWR (-10 -1990))
+  )
+  N(5 I(GND)
+   J(l13 GND (320 8400))
+   J(l13 GND (-50 -7600))
+  )
+  P(1 I(ANY))
+  P(2 I(R))
+  P(3 I(ANY))
+  P(4 I(PWR))
+  P(5 I(GND))
+  X(1 INV2 Y(0 0)
+   P(0 1)
+   P(1 2)
+   P(2 2)
+   P(3 3)
+   P(4 4)
+   P(5 5)
+  )
+ )
+)
+H(
+ K(PMOS MOS3)
+ K(NMOS MOS3)
+ X(INV
+  N(1 I(VDD))
+  N(2 I(VSS))
+  N(3 I(A))
+  N(4 I(Q))
+  P(1 I(VDD))
+  P(2 I(VSS))
+  P(3 I(A))
+  P(4 I(Q))
+  D(1 PMOS
+   I($1)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 1)
+   T(G 3)
+   T(D 4)
+  )
+  D(2 NMOS
+   I($3)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 2)
+   T(G 3)
+   T(D 4)
+  )
+ )
+ X(INV2
+  N(1 I(VDD))
+  N(2 I(VSS))
+  N(3 I(A1))
+  N(4 I(Q1))
+  N(5 I(A2))
+  N(6 I(Q2))
+  P(1 I(VDD))
+  P(2 I(VSS))
+  P(3 I(A1))
+  P(4 I(Q1))
+  P(5 I(A2))
+  P(6 I(Q2))
+  X(1 INV I($1)
+   P(0 1)
+   P(1 2)
+   P(2 3)
+   P(3 4)
+  )
+  X(2 INV I($2)
+   P(0 1)
+   P(1 2)
+   P(2 5)
+   P(3 6)
+  )
+ )
+ X(INVCHAIN
+  N(1 I('1'))
+  N(2 I('2'))
+  N(3 I('3'))
+  N(4 I('4'))
+  N(5 I('5'))
+  X(1 INV2 I($2)
+   P(0 1)
+   P(1 2)
+   P(2 3)
+   P(3 4)
+   P(4 4)
+   P(5 5)
+  )
+ )
+)
+Z(
+ X(INV INV 1
+  Z(
+   N(3 3 1)
+   N(4 4 1)
+   N(2 1 1)
+   N(1 2 1)
+   P(2 2 1)
+   P(3 3 1)
+   P(1 0 1)
+   P(0 1 1)
+   D(2 2 1)
+   D(1 1 1)
+  )
+ )
+ X(INV2 INV2 1
+  Z(
+   N(1 3 1)
+   N(2 5 1)
+   N(3 4 W)
+   N(4 6 W)
+   N(5 1 1)
+   N(6 2 1)
+   P(0 2 1)
+   P(1 4 1)
+   P(2 3 1)
+   P(3 5 1)
+   P(4 0 1)
+   P(5 1 1)
+   X(1 1 1)
+   X(2 2 1)
+  )
+ )
+ X(INVCHAIN INVCHAIN 1
+  Z(
+   N(1 3 1)
+   N(3 5 1)
+   N(5 2 1)
+   N(4 1 1)
+   N(2 4 1)
+   P(2 () 1)
+   P(0 () 1)
+   P(4 () 1)
+   P(3 () 1)
+   P(1 () 1)
+   X(1 1 1)
+  )
+ )
+)