mirror of
https://github.com/KLayout/klayout.git
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Enhanced documentation for blank_circuit, consilidated 'blank_circuit' method provided which can be used anywhere
This commit is contained in:
Matthias Koefferlein
@@ -0,0 +1,70 @@
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* Extracted by KLayout
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* cell RINGO
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* pin FB
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* pin VDD
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* pin OUT
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* pin ENABLE
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* pin VSS
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.SUBCKT RINGO 5 6 7 8 9
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* net 5 FB
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* net 6 VDD
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* net 7 OUT
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* net 8 ENABLE
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* net 9 VSS
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* cell instance $1 r0 *1 1.8,0
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X$1 6 1 9 6 5 8 9 ND2X1
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* cell instance $2 r0 *1 4.2,0
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X$2 6 2 9 6 1 9 INVX1
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* cell instance $3 r0 *1 6,0
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X$3 6 10 9 6 2 9 INVX1
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* cell instance $4 r0 *1 16.8,0
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X$4 6 3 9 6 11 9 INVX1
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* cell instance $5 r0 *1 18.6,0
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X$5 6 4 9 6 3 9 INVX1
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* cell instance $6 r0 *1 20.4,0
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X$6 6 5 9 6 4 9 INVX1
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* cell instance $7 r0 *1 22.2,0
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X$7 5 6 7 9 6 9 INVX2
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* cell instance $17 r0 *1 7.8,0
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X$17 6 12 9 6 10 9 INVX1
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* cell instance $18 r0 *1 9.6,0
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X$18 6 13 9 6 12 9 INVX1
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* cell instance $19 r0 *1 11.4,0
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X$19 6 14 9 6 13 9 INVX1
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* cell instance $20 r0 *1 13.2,0
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X$20 6 15 9 6 14 9 INVX1
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* cell instance $21 r0 *1 15,0
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X$21 6 11 9 6 15 9 INVX1
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.ENDS RINGO
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* cell INVX2
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* pin IN
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin BULK
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.SUBCKT INVX2 1 2 3 4 5 6
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.ENDS INVX2
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* cell INVX1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin IN
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* pin BULK
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.SUBCKT INVX1 1 2 3 4 5 6
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.ENDS INVX1
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* cell ND2X1
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* pin VDD
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* pin OUT
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* pin VSS
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* pin
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* pin B
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* pin A
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* pin BULK
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.SUBCKT ND2X1 1 2 3 4 5 6 7
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.ENDS ND2X1
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@@ -0,0 +1,87 @@
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source($lvs_test_source, "RINGO")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("ringo_for_blackboxing.cir")
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blank_circuit("INVX1")
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blank_circuit("INVX2")
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blank_circuit("ND2X1")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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# and to provide the BULK labels for
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# the abstracts
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bulk = labels(13, 0)
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.flatten_circuit("INVCHAIN")
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netlist.make_top_level_pins
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netlist.purge
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netlist.combine_devices
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netlist.purge_nets
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consider_net_names(false)
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compare
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+540
@@ -0,0 +1,540 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(RINGO)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12 '10/0')
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layer(l13 '11/0')
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layer(l7 '13/0')
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Circuit boundary
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rect((-100 250) (2600 7750))
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# Outgoing pins and their connections to nets
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin()
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pin(name(B))
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pin(name(A))
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pin(name(BULK))
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)
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circuit(INVX1
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# Circuit boundary
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rect((-100 250) (2000 7750))
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# Outgoing pins and their connections to nets
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin()
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pin(name(IN))
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pin(name(BULK))
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)
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circuit(INVX2
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# Circuit boundary
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rect((-100 250) (2600 7750))
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# Outgoing pins and their connections to nets
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pin(name(IN))
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pin(name(VDD))
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pin(name(OUT))
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pin(name(VSS))
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pin()
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pin(name(BULK))
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)
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circuit(RINGO
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# Circuit boundary
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rect((600 250) (25800 7750))
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# Nets with their geometries
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net(1
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rect(l11 (4040 2950) (610 300))
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)
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net(2
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rect(l11 (5550 2950) (900 300))
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)
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net(3
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rect(l11 (18150 2950) (900 300))
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)
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net(4
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rect(l11 (19950 2950) (900 300))
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)
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net(5 name(FB)
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rect(l11 (21750 2950) (900 300))
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rect(l11 (-19530 590) (320 320))
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rect(l11 (17820 -320) (320 320))
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rect(l12 (-18400 -260) (200 200))
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rect(l12 (17940 -200) (200 200))
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rect(l13 (-18040 -300) (17740 400))
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rect(l13 (-17921 -201) (2 2))
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rect(l13 (-221 -201) (400 400))
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rect(l13 (17740 -400) (400 400))
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)
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net(6 name(VDD)
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rect(l3 (1100 4500) (1400 3500))
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rect(l3 (-1900 -3500) (600 3500))
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rect(l3 (23300 -3500) (1400 3500))
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rect(l3 (-100 -3500) (600 3500))
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rect(l8 (-24690 -1240) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (23220 370) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l11 (-22341 859) (2 2))
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rect(l11 (-1751 -451) (1200 800))
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rect(l11 (-750 -1450) (300 1400))
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rect(l11 (-101 -351) (2 2))
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rect(l11 (-1251 -401) (600 800))
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rect(l11 (23400 -800) (1200 800))
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rect(l11 (-750 -1450) (300 1400))
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rect(l11 (-101 -351) (2 2))
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rect(l11 (549 -401) (600 800))
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rect(l9 (-24850 -1500) (500 1500))
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rect(l9 (22900 -1500) (500 1500))
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)
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net(7 name(OUT)
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rect(l11 (23440 3840) (320 320))
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rect(l12 (-260 -260) (200 200))
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rect(l13 (-101 -101) (2 2))
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rect(l13 (-201 -201) (400 400))
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)
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net(8 name(ENABLE)
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rect(l11 (2440 2940) (320 320))
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rect(l12 (-260 -260) (200 200))
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rect(l13 (-101 -101) (2 2))
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rect(l13 (-201 -201) (400 400))
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)
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net(9 name(VSS)
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rect(l8 (1710 1610) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (23220 370) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-22341 -391) (2 2))
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rect(l11 (-1301 -401) (300 1400))
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rect(l11 (-750 -1450) (1200 800))
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rect(l11 (-551 -401) (2 2))
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rect(l11 (-1251 -401) (600 800))
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rect(l11 (23850 -750) (300 1400))
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rect(l11 (-750 -1450) (1200 800))
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rect(l11 (-551 -401) (2 2))
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rect(l11 (549 -401) (600 800))
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rect(l10 (-24850 -800) (500 1500))
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rect(l10 (22900 -1500) (500 1500))
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)
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net(10
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rect(l11 (7350 2950) (900 300))
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)
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net(11
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rect(l11 (16350 2950) (900 300))
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)
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net(12
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rect(l11 (9150 2950) (900 300))
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)
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net(13
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rect(l11 (10950 2950) (900 300))
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)
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net(14
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rect(l11 (12750 2950) (900 300))
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)
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net(15
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rect(l11 (14550 2950) (900 300))
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)
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# Outgoing pins and their connections to nets
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pin(5 name(FB))
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pin(6 name(VDD))
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pin(7 name(OUT))
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pin(8 name(ENABLE))
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pin(9 name(VSS))
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# Subcircuits and their connections
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circuit(1 ND2X1 location(1800 0)
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pin(0 6)
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pin(1 1)
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pin(2 9)
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pin(3 6)
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pin(4 5)
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pin(5 8)
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pin(6 9)
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)
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circuit(2 INVX1 location(4200 0)
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pin(0 6)
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pin(1 2)
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pin(2 9)
|
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pin(3 6)
|
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pin(4 1)
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pin(5 9)
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)
|
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circuit(3 INVX1 location(6000 0)
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pin(0 6)
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pin(1 10)
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||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 2)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(4 INVX1 location(16800 0)
|
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pin(0 6)
|
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pin(1 3)
|
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pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 11)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(5 INVX1 location(18600 0)
|
||||
pin(0 6)
|
||||
pin(1 4)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
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pin(4 3)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(6 INVX1 location(20400 0)
|
||||
pin(0 6)
|
||||
pin(1 5)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 4)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(7 INVX2 location(22200 0)
|
||||
pin(0 5)
|
||||
pin(1 6)
|
||||
pin(2 7)
|
||||
pin(3 9)
|
||||
pin(4 6)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(17 INVX1 location(7800 0)
|
||||
pin(0 6)
|
||||
pin(1 12)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 10)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(18 INVX1 location(9600 0)
|
||||
pin(0 6)
|
||||
pin(1 13)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 12)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(19 INVX1 location(11400 0)
|
||||
pin(0 6)
|
||||
pin(1 14)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 13)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(20 INVX1 location(13200 0)
|
||||
pin(0 6)
|
||||
pin(1 15)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 14)
|
||||
pin(5 9)
|
||||
)
|
||||
circuit(21 INVX1 location(15000 0)
|
||||
pin(0 6)
|
||||
pin(1 11)
|
||||
pin(2 9)
|
||||
pin(3 6)
|
||||
pin(4 15)
|
||||
pin(5 9)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin(name(NWELL))
|
||||
pin(name(B))
|
||||
pin(name(A))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(INVX1
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin(name(NWELL))
|
||||
pin(name(IN))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(INVX2
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(name(VDD))
|
||||
pin(name(OUT))
|
||||
pin(name(VSS))
|
||||
pin(name(NWELL))
|
||||
pin(name(IN))
|
||||
pin(name(BULK))
|
||||
|
||||
)
|
||||
circuit(RINGO
|
||||
|
||||
# Nets
|
||||
net(1 name(VSS))
|
||||
net(2 name(VDD))
|
||||
net(3 name(FB))
|
||||
net(4 name(ENABLE))
|
||||
net(5 name(OUT))
|
||||
net(6 name('1'))
|
||||
net(7 name('2'))
|
||||
net(8 name('3'))
|
||||
net(9 name('4'))
|
||||
net(10 name('5'))
|
||||
net(11 name('6'))
|
||||
net(12 name('7'))
|
||||
net(13 name('8'))
|
||||
net(14 name('9'))
|
||||
net(15 name('10'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VSS))
|
||||
pin(2 name(VDD))
|
||||
pin(3 name(FB))
|
||||
pin(4 name(ENABLE))
|
||||
pin(5 name(OUT))
|
||||
|
||||
# Subcircuits and their connections
|
||||
circuit(1 ND2X1 name($1)
|
||||
pin(0 2)
|
||||
pin(1 6)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 4)
|
||||
pin(6 1)
|
||||
)
|
||||
circuit(2 INVX1 name($2)
|
||||
pin(0 2)
|
||||
pin(1 7)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 6)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(3 INVX1 name($3)
|
||||
pin(0 2)
|
||||
pin(1 8)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 7)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(4 INVX1 name($4)
|
||||
pin(0 2)
|
||||
pin(1 9)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 8)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(5 INVX1 name($5)
|
||||
pin(0 2)
|
||||
pin(1 10)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 9)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(6 INVX1 name($6)
|
||||
pin(0 2)
|
||||
pin(1 11)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 10)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(7 INVX1 name($7)
|
||||
pin(0 2)
|
||||
pin(1 12)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 11)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(8 INVX1 name($8)
|
||||
pin(0 2)
|
||||
pin(1 13)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 12)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(9 INVX1 name($9)
|
||||
pin(0 2)
|
||||
pin(1 14)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 13)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(10 INVX1 name($10)
|
||||
pin(0 2)
|
||||
pin(1 15)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 14)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(11 INVX1 name($11)
|
||||
pin(0 2)
|
||||
pin(1 3)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 15)
|
||||
pin(5 1)
|
||||
)
|
||||
circuit(12 INVX2 name($12)
|
||||
pin(0 2)
|
||||
pin(1 5)
|
||||
pin(2 1)
|
||||
pin(3 2)
|
||||
pin(4 3)
|
||||
pin(5 1)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(INVX1 INVX1 match
|
||||
xref(
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(1 1 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(INVX2 INVX2 match
|
||||
xref(
|
||||
pin(4 3 match)
|
||||
pin(5 5 match)
|
||||
pin(0 4 match)
|
||||
pin(2 1 match)
|
||||
pin(1 0 match)
|
||||
pin(3 2 match)
|
||||
)
|
||||
)
|
||||
circuit(ND2X1 ND2X1 match
|
||||
xref(
|
||||
pin(3 3 match)
|
||||
pin(5 5 match)
|
||||
pin(4 4 match)
|
||||
pin(6 6 match)
|
||||
pin(1 1 match)
|
||||
pin(0 0 match)
|
||||
pin(2 2 match)
|
||||
)
|
||||
)
|
||||
circuit(RINGO RINGO match
|
||||
xref(
|
||||
net(1 6 match)
|
||||
net(4 15 match)
|
||||
net(2 7 match)
|
||||
net(10 8 match)
|
||||
net(12 9 match)
|
||||
net(13 10 match)
|
||||
net(14 11 match)
|
||||
net(15 12 match)
|
||||
net(11 13 match)
|
||||
net(3 14 match)
|
||||
net(8 4 match)
|
||||
net(5 3 match)
|
||||
net(7 5 match)
|
||||
net(6 2 match)
|
||||
net(9 1 match)
|
||||
pin(3 3 match)
|
||||
pin(0 2 match)
|
||||
pin(2 4 match)
|
||||
pin(1 1 match)
|
||||
pin(4 0 match)
|
||||
circuit(2 2 match)
|
||||
circuit(3 3 match)
|
||||
circuit(17 4 match)
|
||||
circuit(18 5 match)
|
||||
circuit(19 6 match)
|
||||
circuit(20 7 match)
|
||||
circuit(21 8 match)
|
||||
circuit(4 9 match)
|
||||
circuit(5 10 match)
|
||||
circuit(6 11 match)
|
||||
circuit(7 12 match)
|
||||
circuit(1 1 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
Reference in New Issue
Block a user