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Introduced perimeter parameters for MOS3/MOS4

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This commit is contained in:
Matthias Koefferlein
2019-02-02 01:29:28 +01:00
parent 11cfe36ed1
commit c90f7e4af9
21 changed files with 278 additions and 159 deletions
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testdata/algo/l2n_writer_au.txt
Vendored
+8
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@@ -162,6 +162,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.49875)
param(AD 0.26125)
param(PS 2.95)
param(PD 1.5)
terminal(S $2)
terminal(G IN)
terminal(D $5)
@@ -172,6 +174,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.26125)
param(AD 0.49875)
param(PS 1.5)
param(PD 2.95)
terminal(S $5)
terminal(G $2)
terminal(D OUT)
@@ -182,6 +186,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.49875)
param(AD 0.26125)
param(PS 2.95)
param(PD 1.5)
terminal(S $2)
terminal(G IN)
terminal(D $4)
@@ -192,6 +198,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.26125)
param(AD 0.49875)
param(PS 1.5)
param(PD 2.95)
terminal(S $4)
terminal(G $2)
terminal(D OUT)
testdata/algo/l2n_writer_au_2.txt
Vendored
+8
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@@ -198,6 +198,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.49875)
param(AD 0.26125)
param(PS 2.95)
param(PD 1.5)
terminal(S $3)
terminal(G IN)
terminal(D VDD)
@@ -209,6 +211,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.26125)
param(AD 0.49875)
param(PS 1.5)
param(PD 2.95)
terminal(S VDD)
terminal(G $3)
terminal(D OUT)
@@ -220,6 +224,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.49875)
param(AD 0.26125)
param(PS 2.95)
param(PD 1.5)
terminal(S $3)
terminal(G IN)
terminal(D VSS)
@@ -231,6 +237,8 @@ circuit(INV2
param(W 0.95)
param(AS 0.26125)
param(AD 0.49875)
param(PS 1.5)
param(PD 2.95)
terminal(S VSS)
terminal(G $3)
terminal(D OUT)
testdata/algo/l2n_writer_au_2s.txt
Vendored
+8
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@@ -174,6 +174,8 @@ X(INV2
E(W 0.95)
E(AS 0.49875)
E(AD 0.26125)
E(PS 2.95)
E(PD 1.5)
T(S $3)
T(G IN)
T(D VDD)
@@ -185,6 +187,8 @@ X(INV2
E(W 0.95)
E(AS 0.26125)
E(AD 0.49875)
E(PS 1.5)
E(PD 2.95)
T(S VDD)
T(G $3)
T(D OUT)
@@ -196,6 +200,8 @@ X(INV2
E(W 0.95)
E(AS 0.49875)
E(AD 0.26125)
E(PS 2.95)
E(PD 1.5)
T(S $3)
T(G IN)
T(D VSS)
@@ -207,6 +213,8 @@ X(INV2
E(W 0.95)
E(AS 0.26125)
E(AD 0.49875)
E(PS 1.5)
E(PD 2.95)
T(S VSS)
T(G $3)
T(D OUT)
testdata/algo/l2n_writer_au_s.txt
Vendored
+8
View File
@@ -140,6 +140,8 @@ X(INV2
E(W 0.95)
E(AS 0.49875)
E(AD 0.26125)
E(PS 2.95)
E(PD 1.5)
T(S $2)
T(G IN)
T(D $5)
@@ -150,6 +152,8 @@ X(INV2
E(W 0.95)
E(AS 0.26125)
E(AD 0.49875)
E(PS 1.5)
E(PD 2.95)
T(S $5)
T(G $2)
T(D OUT)
@@ -160,6 +164,8 @@ X(INV2
E(W 0.95)
E(AS 0.49875)
E(AD 0.26125)
E(PS 2.95)
E(PD 1.5)
T(S $2)
T(G IN)
T(D $4)
@@ -170,6 +176,8 @@ X(INV2
E(W 0.95)
E(AS 0.26125)
E(AD 0.49875)
E(PS 1.5)
E(PD 2.95)
T(S $4)
T(G $2)
T(D OUT)
testdata/algo/nwriter5_au.txt
Vendored
+2 -2
View File
@@ -10,7 +10,7 @@
* net 3 n3
* net 4 n4
* device instance $1 0,0 M3CLS
M$1 1 4 3 1 MM3CLS L=0.25U W=0.18U AS=1.2U AD=0.75U
M$1 1 4 3 1 MM3CLS L=0.25U W=0.18U AS=1.2U AD=0.75U PS=2.2U PD=1.75U
* device instance $2 0,0 M3CLS
M$2 3 4 2 3 MM3CLS L=1.4U W=0.25U AS=1.3U AD=0.85U
M$2 3 4 2 3 MM3CLS L=1.4U W=0.25U AS=1.3U AD=0.85U PS=2.3U PD=1.85U
.ENDS C1
testdata/algo/nwriter6_au.txt
Vendored
+2 -2
View File
@@ -12,7 +12,7 @@
* net 4 n4
* net 5 n5
* device instance $1 0,0 M4CLS
M$1 1 4 3 5 1 MM4CLS L=0.25U W=0.18U AS=1.2U AD=0.75U
M$1 1 4 3 5 1 MM4CLS L=0.25U W=0.18U AS=1.2U AD=0.75U PS=2.2U PD=1.75U
* device instance $2 0,0 M4CLS
M$2 3 4 2 5 3 MM4CLS L=1.4U W=0.25U AS=1.3U AD=0.85U
M$2 3 4 2 5 3 MM4CLS L=1.4U W=0.25U AS=1.3U AD=0.85U PS=2.3U PD=1.85U
.ENDS C1
testdata/algo/nwriter8_au.txt
Vendored
+2 -2
View File
@@ -28,7 +28,7 @@ XSC2 3 2 4 3 C1
* net 4 n4
* net 5 n5
* device instance $1 0,0 M4CLS
M$1 1 4 3 5 1 MM4CLS L=0.25U W=0.18U AS=1.2U AD=0.75U
M$1 1 4 3 5 1 MM4CLS L=0.25U W=0.18U AS=1.2U AD=0.75U PS=2.2U PD=1.75U
* device instance $2 0,0 M4CLS
M$2 3 4 2 5 3 MM4CLS L=1.4U W=0.25U AS=1.3U AD=0.85U
M$2 3 4 2 5 3 MM4CLS L=1.4U W=0.25U AS=1.3U AD=0.85U PS=2.3U PD=1.85U
.ENDS C1
testdata/ruby/dbLayoutToNetlist.rb
Vendored
+12 -12
View File
@@ -279,10 +279,10 @@ Circuit RINGO ():
XINV2 $9 (IN=$I6,$2=$I45,OUT=$I7,$4=VSS,$5=VDD)
XINV2 $10 (IN=$I7,$2=$I46,OUT=$I8,$4=VSS,$5=VDD)
Circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5):
DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
DPMOS $1 (S=$2,G=IN,D=$5) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
DPMOS $2 (S=$5,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
DNMOS $3 (S=$2,G=IN,D=$4) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
DNMOS $4 (S=$4,G=$2,D=OUT) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
XTRANS $1 ($1=$2,$2=$4,$3=IN)
XTRANS $2 ($1=$2,$2=$5,$3=IN)
XTRANS $3 ($1=$5,$2=OUT,$3=$2)
@@ -390,10 +390,10 @@ Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
XINV2 $1 ($1=$I1,IN=$I3,$3=$I7,OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
XTRANS $1 ($1=$3,$2=VSS,$3=IN)
XTRANS $2 ($1=$3,$2=VDD,$3=IN)
XTRANS $3 ($1=VDD,$2=OUT,$3=$3)
@@ -416,10 +416,10 @@ Circuit INV2PAIR (BULK=BULK,$2=$I8,$3=$I6,$4=$I5,$5=$I3,$6=$I2,$7=$I1):
XINV2 $1 ($1=$I1,IN=$I3,$3=(null),OUT=$I4,VSS=$I5,VDD=$I6,BULK=BULK)
XINV2 $2 ($1=$I1,IN=$I4,$3=$I8,OUT=$I2,VSS=$I5,VDD=$I6,BULK=BULK)
Circuit INV2 ($1=$1,IN=IN,$3=$3,OUT=OUT,VSS=VSS,VDD=VDD,BULK=BULK):
DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125]
DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875]
DPMOS $1 (S=$3,G=IN,D=VDD,B=$1) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
DPMOS $2 (S=VDD,G=$3,D=OUT,B=$1) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
DNMOS $3 (S=$3,G=IN,D=VSS,B=BULK) [L=0.25,W=0.95,AS=0.49875,AD=0.26125,PS=2.95,PD=1.5]
DNMOS $4 (S=VSS,G=$3,D=OUT,B=BULK) [L=0.25,W=0.95,AS=0.26125,AD=0.49875,PS=1.5,PD=2.95]
END
# cleanup now
testdata/ruby/dbNetlistDeviceClasses.rb
Vendored
+14 -6
View File
@@ -222,11 +222,15 @@ END
d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_W, 2.0)
d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_AS, 3.0)
d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_AD, 4.0)
d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_PS, 13.0)
d1.set_parameter(RBA::DeviceClassMOS3Transistor::PARAM_PD, 14.0)
d2 = circuit.create_device(cls, "d2")
d2.set_parameter("L", 1.0)
d2.set_parameter("W", 3.0)
d2.set_parameter("AS", 4.0)
d2.set_parameter("AD", 5.0)
d2.set_parameter("PS", 14.0)
d2.set_parameter("PD", 15.0)
pin_a = circuit.create_pin ("A")
pin_b = circuit.create_pin ("B")
@@ -249,8 +253,8 @@ END
assert_equal(nl.to_s, <<END)
Circuit (A=n1,B=n2,C=n3):
D d1 (S=n1,G=n3,D=n2) [L=1,W=2,AS=3,AD=4]
D d2 (S=n1,G=n3,D=n2) [L=1,W=3,AS=4,AD=5]
D d1 (S=n1,G=n3,D=n2) [L=1,W=2,AS=3,AD=4,PS=13,PD=14]
D d2 (S=n1,G=n3,D=n2) [L=1,W=3,AS=4,AD=5,PS=14,PD=15]
END
nl.combine_devices
@@ -258,7 +262,7 @@ END
assert_equal(nl.to_s, <<END)
Circuit (A=n1,B=n2,C=n3):
D d1 (S=n1,G=n3,D=n2) [L=1,W=5,AS=7,AD=9]
D d1 (S=n1,G=n3,D=n2) [L=1,W=5,AS=7,AD=9,PS=27,PD=29]
END
end
@@ -278,11 +282,15 @@ END
d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_W, 2.0)
d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_AS, 3.0)
d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_AD, 4.0)
d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_PS, 13.0)
d1.set_parameter(RBA::DeviceClassMOS4Transistor::PARAM_PD, 14.0)
d2 = circuit.create_device(cls, "d2")
d2.set_parameter("L", 1.0)
d2.set_parameter("W", 3.0)
d2.set_parameter("AS", 4.0)
d2.set_parameter("AD", 5.0)
d2.set_parameter("PS", 14.0)
d2.set_parameter("PD", 15.0)
pin_a = circuit.create_pin ("A")
pin_b = circuit.create_pin ("B")
@@ -311,8 +319,8 @@ END
assert_equal(nl.to_s, <<END)
Circuit (A=n1,B=n2,C=n3,D=n4):
D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=2,AS=3,AD=4]
D d2 (S=n1,G=n3,D=n2,B=n4) [L=1,W=3,AS=4,AD=5]
D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=2,AS=3,AD=4,PS=13,PD=14]
D d2 (S=n1,G=n3,D=n2,B=n4) [L=1,W=3,AS=4,AD=5,PS=14,PD=15]
END
nl.combine_devices
@@ -320,7 +328,7 @@ END
assert_equal(nl.to_s, <<END)
Circuit (A=n1,B=n2,C=n3,D=n4):
D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=5,AS=7,AD=9]
D d1 (S=n1,G=n3,D=n2,B=n4) [L=1,W=5,AS=7,AD=9,PS=27,PD=29]
END
end