From a91c3d3a4e8be93dce65f902a6d18148ca7c5e88 Mon Sep 17 00:00:00 2001
From: Matthias Koefferlein <matthias@koefferlein.de>
Date: Sat, 15 Jun 2019 21:11:15 +0200
Subject: [PATCH] WIP: fixed BJT4 class, added RBA tests for new device
 classes.

---
 src/db/db/dbNetlistDeviceClasses.cc           |  25 +-
 .../unit_tests/dbNetlistDeviceClassesTests.cc |  92 +++++++
 testdata/ruby/dbNetlistDeviceClasses.rb       | 260 +++++++++++++++++-
 3 files changed, 367 insertions(+), 10 deletions(-)

diff --git a/src/db/db/dbNetlistDeviceClasses.cc b/src/db/db/dbNetlistDeviceClasses.cc
index f4dd10f60..d09a330b0 100644
--- a/src/db/db/dbNetlistDeviceClasses.cc
+++ b/src/db/db/dbNetlistDeviceClasses.cc
@@ -546,15 +546,30 @@ DeviceClassBJT4Transistor::DeviceClassBJT4Transistor ()
 
 bool DeviceClassBJT4Transistor::combine_devices (Device *a, Device *b) const
 {
+  const db::Net *nac = a->net_for_terminal (0);
+  const db::Net *nab = a->net_for_terminal (1);
+  const db::Net *nae = a->net_for_terminal (2);
   const db::Net *nas = a->net_for_terminal (3);
+  const db::Net *nbc = b->net_for_terminal (0);
+  const db::Net *nbb = b->net_for_terminal (1);
+  const db::Net *nbe = b->net_for_terminal (2);
   const db::Net *nbs = b->net_for_terminal (3);
 
-  //  combination is possible only if the substrate nets are the same
-  if (nas == nbs) {
-    return combine_devices (a, b);
-  } else {
-    return false;
+  //  parallel transistors can be combined into one
+  if (nac == nbc && nae == nbe && nab == nbb && nas == nbs) {
+
+    combine_parameters (a, b);
+
+    a->join_terminals (0, b, 0);
+    a->join_terminals (1, b, 1);
+    a->join_terminals (2, b, 2);
+    a->join_terminals (3, b, 3);
+
+    return true;
+
   }
+
+  return false;
 }
 
 }
diff --git a/src/db/unit_tests/dbNetlistDeviceClassesTests.cc b/src/db/unit_tests/dbNetlistDeviceClassesTests.cc
index 83bf957bd..b4ba6748c 100644
--- a/src/db/unit_tests/dbNetlistDeviceClassesTests.cc
+++ b/src/db/unit_tests/dbNetlistDeviceClassesTests.cc
@@ -2107,3 +2107,95 @@ TEST(39_ParallelBJT3Transistors)
   );
 }
 
+TEST(40_ParallelBJT4Transistors)
+{
+  db::DeviceClassBJT4Transistor *cls = new db::DeviceClassBJT4Transistor ();
+
+  db::Netlist nl;
+  nl.add_device_class (cls);
+
+  db::Device *d1 = new db::Device (cls, "d1");
+  d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AE, 2.0);
+  d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PE, 12.0);
+  d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AB, 3.0);
+  d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PB, 13.0);
+  d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AC, 4.0);
+  d1->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PC, 14.0);
+  db::Device *d2 = new db::Device (cls, "d2");
+  d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AE, 3.0);
+  d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PE, 13.0);
+  d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AB, 4.0);
+  d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PB, 14.0);
+  d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_AC, 5.0);
+  d2->set_parameter_value (db::DeviceClassBJT4Transistor::param_id_PC, 15.0);
+
+  db::Circuit *circuit = new db::Circuit ();
+  nl.add_circuit (circuit);
+
+  db::Pin pin_a = circuit->add_pin ("A");
+  db::Pin pin_b = circuit->add_pin ("B");
+  db::Pin pin_c = circuit->add_pin ("C");
+  db::Pin pin_d = circuit->add_pin ("D");
+
+  circuit->add_device (d1);
+  circuit->add_device (d2);
+
+  db::Net *n1 = new db::Net ("n1");
+  circuit->add_net (n1);
+  circuit->connect_pin (pin_a.id (), n1);
+  d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_C, n1);
+  d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_C, n1);
+
+  db::Net *n2 = new db::Net ("n2");
+  circuit->add_net (n2);
+  circuit->connect_pin (pin_b.id (), n2);
+  d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_B, n2);
+  d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_B, n2);
+  d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_E, n2);
+
+  db::Net *n3 = new db::Net ("n3");
+  circuit->add_net (n3);
+  circuit->connect_pin (pin_c.id (), n3);
+  d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_E, n3);
+
+  db::Net *n4 = new db::Net ("n4");
+  circuit->add_net (n4);
+  circuit->connect_pin (pin_d.id (), n4);
+  d1->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_S, n4);
+  d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_S, n4);
+
+  EXPECT_EQ (nl.to_string (),
+    "circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
+    "  device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=2,PE=12,AB=3,PB=13,AC=4,PC=14);\n"
+    "  device '' d2 (C=n1,B=n2,E=n2,S=n4) (AE=3,PE=13,AB=4,PB=14,AC=5,PC=15);\n"
+    "end;\n"
+  );
+
+  nl.combine_devices ();
+
+  //  no combination as emitters are connected differently
+  EXPECT_EQ (nl.to_string (),
+    "circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
+    "  device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=2,PE=12,AB=3,PB=13,AC=4,PC=14);\n"
+    "  device '' d2 (C=n1,B=n2,E=n2,S=n4) (AE=3,PE=13,AB=4,PB=14,AC=5,PC=15);\n"
+    "end;\n"
+  );
+
+  d2->connect_terminal (db::DeviceClassBJT4Transistor::terminal_id_E, n3);
+
+  EXPECT_EQ (nl.to_string (),
+    "circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
+    "  device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=2,PE=12,AB=3,PB=13,AC=4,PC=14);\n"
+    "  device '' d2 (C=n1,B=n2,E=n3,S=n4) (AE=3,PE=13,AB=4,PB=14,AC=5,PC=15);\n"
+    "end;\n"
+  );
+
+  nl.combine_devices ();
+
+  EXPECT_EQ (nl.to_string (),
+    "circuit '' (A=n1,B=n2,C=n3,D=n4);\n"
+    "  device '' d1 (C=n1,B=n2,E=n3,S=n4) (AE=5,PE=25,AB=7,PB=27,AC=9,PC=29);\n"
+    "end;\n"
+  );
+}
+
diff --git a/testdata/ruby/dbNetlistDeviceClasses.rb b/testdata/ruby/dbNetlistDeviceClasses.rb
index fda223a36..57da3371a 100644
--- a/testdata/ruby/dbNetlistDeviceClasses.rb
+++ b/testdata/ruby/dbNetlistDeviceClasses.rb
@@ -37,6 +37,10 @@ class DBNetlistDeviceClasses_TestClass < TestBase
 
     r1 = circuit.create_device(cls, "r1")
     r1.set_parameter(RBA::DeviceClassResistor::PARAM_R, 1.0)
+    r1.set_parameter(RBA::DeviceClassResistor::PARAM_L, 10.0)
+    r1.set_parameter(RBA::DeviceClassResistor::PARAM_W, 11.0)
+    r1.set_parameter(RBA::DeviceClassResistor::PARAM_A, 12.0)
+    r1.set_parameter(RBA::DeviceClassResistor::PARAM_P, 13.0)
     r2 = circuit.create_device(cls, "r2")
     r2.set_parameter("R", 3.0)
 
@@ -57,8 +61,8 @@ class DBNetlistDeviceClasses_TestClass < TestBase
 
     assert_equal(nl.to_s, <<END)
 circuit '' (A=n1,B=n3);
-  device '' r1 (A=n1,B=n2) (R=1,A=0,P=0);
-  device '' r2 (A=n2,B=n3) (R=3,A=0,P=0);
+  device '' r1 (A=n1,B=n2) (R=1,L=10,W=11,A=12,P=13);
+  device '' r2 (A=n2,B=n3) (R=3,L=0,W=0,A=0,P=0);
 end;
 END
 
@@ -67,7 +71,65 @@ END
 
     assert_equal(nl.to_s, <<END)
 circuit '' (A=n1,B=n3);
-  device '' r1 (A=n1,B=n3) (R=4,A=0,P=0);
+  device '' r1 (A=n1,B=n3) (R=4,L=10,W=11,A=12,P=13);
+end;
+END
+
+  end
+
+  def test_1_ResistorsWithBulk
+  
+    cls = RBA::DeviceClassResistorWithBulk::new
+
+    nl = RBA::Netlist::new
+    nl.add(cls)
+
+    circuit = RBA::Circuit::new
+    nl.add(circuit)
+
+    r1 = circuit.create_device(cls, "r1")
+    r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_R, 1.0)
+    r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_L, 10.0)
+    r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_W, 11.0)
+    r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_A, 12.0)
+    r1.set_parameter(RBA::DeviceClassResistorWithBulk::PARAM_P, 13.0)
+    r2 = circuit.create_device(cls, "r2")
+    r2.set_parameter("R", 3.0)
+
+    pin_a = circuit.create_pin ("A")
+    pin_b = circuit.create_pin ("B")
+    pin_bulk = circuit.create_pin ("BULK")
+
+    n1 = circuit.create_net("n1")
+    circuit.connect_pin(pin_a, n1)
+    r1.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_A, n1)
+
+    n2 = circuit.create_net("n2")
+    r1.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_B, n2)
+    r2.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_A, n2)
+
+    n3 = circuit.create_net("n3")
+    r2.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_B, n3)
+    circuit.connect_pin(pin_b, n3)
+
+    nb = circuit.create_net("nb")
+    r1.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_W, nb)
+    r2.connect_terminal(RBA::DeviceClassResistorWithBulk::TERMINAL_W, nb)
+    circuit.connect_pin(pin_bulk, nb)
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n3,BULK=nb);
+  device '' r1 (A=n1,B=n2,W=nb) (R=1,L=10,W=11,A=12,P=13);
+  device '' r2 (A=n2,B=n3,W=nb) (R=3,L=0,W=0,A=0,P=0);
+end;
+END
+
+    nl.combine_devices
+    nl.purge
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n3,BULK=nb);
+  device '' r1 (A=n1,B=n3,W=nb) (R=4,L=10,W=11,A=12,P=13);
 end;
 END
 
@@ -85,6 +147,8 @@ END
 
     c1 = circuit.create_device(cls, "c1")
     c1.set_parameter(RBA::DeviceClassCapacitor::PARAM_C, 2.0)
+    c1.set_parameter(RBA::DeviceClassCapacitor::PARAM_A, 10.0)
+    c1.set_parameter(RBA::DeviceClassCapacitor::PARAM_P, 11.0)
     c2 = circuit.create_device(cls, "c2")
     c2.set_parameter("C", 3.0)
 
@@ -105,7 +169,7 @@ END
 
     assert_equal(nl.to_s, <<END)
 circuit '' (A=n1,B=n3);
-  device '' c1 (A=n1,B=n2) (C=2,A=0,P=0);
+  device '' c1 (A=n1,B=n2) (C=2,A=10,P=11);
   device '' c2 (A=n2,B=n3) (C=3,A=0,P=0);
 end;
 END
@@ -115,7 +179,63 @@ END
 
     assert_equal(nl.to_s, <<END)
 circuit '' (A=n1,B=n3);
-  device '' c1 (A=n1,B=n3) (C=1.2,A=0,P=0);
+  device '' c1 (A=n1,B=n3) (C=1.2,A=10,P=11);
+end;
+END
+
+  end
+
+  def test_2_CapacitorsWithBulk
+  
+    cls = RBA::DeviceClassCapacitorWithBulk::new
+
+    nl = RBA::Netlist::new
+    nl.add(cls)
+
+    circuit = RBA::Circuit::new
+    nl.add(circuit)
+
+    c1 = circuit.create_device(cls, "c1")
+    c1.set_parameter(RBA::DeviceClassCapacitorWithBulk::PARAM_C, 2.0)
+    c1.set_parameter(RBA::DeviceClassCapacitorWithBulk::PARAM_A, 10.0)
+    c1.set_parameter(RBA::DeviceClassCapacitorWithBulk::PARAM_P, 11.0)
+    c2 = circuit.create_device(cls, "c2")
+    c2.set_parameter("C", 3.0)
+
+    pin_a = circuit.create_pin ("A")
+    pin_b = circuit.create_pin ("B")
+    pin_bulk = circuit.create_pin ("BULK")
+
+    n1 = circuit.create_net("n1")
+    circuit.connect_pin(pin_a, n1)
+    c1.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_A, n1)
+
+    n2 = circuit.create_net("n2")
+    c1.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_B, n2)
+    c2.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_A, n2)
+
+    n3 = circuit.create_net("n3")
+    c2.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_B, n3)
+    circuit.connect_pin(pin_b, n3)
+
+    nb = circuit.create_net("nb")
+    c1.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_W, nb)
+    c2.connect_terminal(RBA::DeviceClassCapacitorWithBulk::TERMINAL_W, nb)
+    circuit.connect_pin(pin_bulk, nb)
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n3,BULK=nb);
+  device '' c1 (A=n1,B=n2,W=nb) (C=2,A=10,P=11);
+  device '' c2 (A=n2,B=n3,W=nb) (C=3,A=0,P=0);
+end;
+END
+
+    nl.combine_devices
+    nl.purge
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n3,BULK=nb);
+  device '' c1 (A=n1,B=n3,W=nb) (C=1.2,A=10,P=11);
 end;
 END
 
@@ -343,6 +463,136 @@ END
 circuit '' (A=n1,B=n2,C=n3,D=n4);
   device '' d1 (S=n1,G=n3,D=n2,B=n4) (L=1,W=5,AS=7,AD=9,PS=27,PD=29);
 end;
+END
+
+  end
+
+  def test_7_BJT3
+  
+    cls = RBA::DeviceClassBJT3Transistor::new
+
+    nl = RBA::Netlist::new
+    nl.add(cls)
+
+    circuit = RBA::Circuit::new
+    nl.add(circuit)
+
+    d1 = circuit.create_device(cls, "d1")
+    d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_AE, 1.0)
+    d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_AB, 2.0)
+    d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_AC, 3.0)
+    d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PE, 12.0)
+    d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PB, 13.0)
+    d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PC, 14.0)
+    d2 = circuit.create_device(cls, "d2")
+    d2.set_parameter("AE", 2.0)
+    d2.set_parameter("AB", 3.0)
+    d2.set_parameter("AC", 4.0)
+    d2.set_parameter("PE", 13.0)
+    d2.set_parameter("PB", 14.0)
+    d2.set_parameter("PC", 15.0)
+
+    pin_a = circuit.create_pin ("A")
+    pin_b = circuit.create_pin ("B")
+    pin_c = circuit.create_pin ("C")
+
+    n1 = circuit.create_net("n1")
+    circuit.connect_pin(pin_a, n1)
+    d1.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_C, n1)
+    d2.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_C, n1)
+
+    n2 = circuit.create_net("n2")
+    circuit.connect_pin(pin_b, n2)
+    d1.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_E, n2)
+    d2.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_E, n2)
+
+    n3 = circuit.create_net("n3")
+    circuit.connect_pin(pin_c, n3)
+    d1.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_B, n3)
+    d2.connect_terminal(RBA::DeviceClassBJT3Transistor::TERMINAL_B, n3)
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n2,C=n3);
+  device '' d1 (C=n1,B=n3,E=n2) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14);
+  device '' d2 (C=n1,B=n3,E=n2) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15);
+end;
+END
+
+    nl.combine_devices
+    nl.purge
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n2,C=n3);
+  device '' d1 (C=n1,B=n3,E=n2) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29);
+end;
+END
+
+  end
+
+  def test_8_BJT4
+  
+    cls = RBA::DeviceClassBJT4Transistor::new
+
+    nl = RBA::Netlist::new
+    nl.add(cls)
+
+    circuit = RBA::Circuit::new
+    nl.add(circuit)
+
+    d1 = circuit.create_device(cls, "d1")
+    d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_AE, 1.0)
+    d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_AB, 2.0)
+    d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_AC, 3.0)
+    d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_PE, 12.0)
+    d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_PB, 13.0)
+    d1.set_parameter(RBA::DeviceClassBJT4Transistor::PARAM_PC, 14.0)
+    d2 = circuit.create_device(cls, "d2")
+    d2.set_parameter("AE", 2.0)
+    d2.set_parameter("AB", 3.0)
+    d2.set_parameter("AC", 4.0)
+    d2.set_parameter("PE", 13.0)
+    d2.set_parameter("PB", 14.0)
+    d2.set_parameter("PC", 15.0)
+
+    pin_a = circuit.create_pin ("A")
+    pin_b = circuit.create_pin ("B")
+    pin_c = circuit.create_pin ("C")
+    pin_d = circuit.create_pin ("D")
+
+    n1 = circuit.create_net("n1")
+    circuit.connect_pin(pin_a, n1)
+    d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_C, n1)
+    d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_C, n1)
+
+    n2 = circuit.create_net("n2")
+    circuit.connect_pin(pin_b, n2)
+    d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_E, n2)
+    d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_E, n2)
+
+    n3 = circuit.create_net("n3")
+    circuit.connect_pin(pin_c, n3)
+    d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_B, n3)
+    d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_B, n3)
+
+    n4 = circuit.create_net("n4")
+    circuit.connect_pin(pin_d, n4)
+    d1.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_S, n4)
+    d2.connect_terminal(RBA::DeviceClassBJT4Transistor::TERMINAL_S, n4)
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n2,C=n3,D=n4);
+  device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14);
+  device '' d2 (C=n1,B=n3,E=n2,S=n4) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15);
+end;
+END
+
+    nl.combine_devices
+    nl.purge
+
+    assert_equal(nl.to_s, <<END)
+circuit '' (A=n1,B=n2,C=n3,D=n4);
+  device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29);
+end;
 END
 
   end