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Added one more testcase for join_symmetric_nets

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Matthias Koefferlein 2020-03-28 09:49:41 +01:00
parent 9afcec25bc
commit a47932a79e
1 changed files with 43 additions and 0 deletions
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43
src/db/unit_tests/dbNetlistCompareTests.cc
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@ -3943,3 +3943,46 @@ TEST(28_NoSymmetryDetectionCases)
} }
} }
TEST(28_JoinSymmetricNets)
{
const char *nls =
"circuit INV2LOAD (A=A,VSS=VSS,VDD=VDD);\n"
" device PMOS $1 (S=OUT1,G=A,D=VDD) (L=0.25,W=1);\n"
" device PMOS $2 (S=VDD,G=A,D=OUT1) (L=0.25,W=1);\n"
" device NMOS $3 (S=VSS,G=A,D=OUT1) (L=0.25,W=1);\n"
" device NMOS $4 (S=VSS,G=A,D=OUT1) (L=0.25,W=1.5);\n"
" device PMOS $5 (S=OUT2,G=A,D=VDD) (L=0.25,W=1);\n"
" device PMOS $6 (S=VDD,G=A,D=OUT2) (L=0.25,W=1);\n"
" device NMOS $7 (S=OUT2,G=A,D=VSS) (L=0.25,W=1);\n"
" device NMOS $8 (S=OUT2,G=A,D=VSS) (L=0.25,W=1);\n"
" device PMOS $9 (S=OUT3,G=A,D=VDD) (L=0.25,W=1);\n"
" device PMOS $10 (S=VDD,G=A,D=OUT3) (L=0.25,W=1);\n"
" device NMOS $11 (S=VSS,G=A,D=OUT3) (L=0.25,W=1);\n"
" device NMOS $12 (S=OUT3,G=A,D=VSS) (L=0.25,W=1);\n"
"end;\n";
db::Netlist nl;
prep_nl (nl, nls);
db::NetlistComparer comp;
comp.join_symmetric_nets (nl.circuit_by_name ("INV2LOAD"));
// NOTE $1 and $2 are joined because they are symmetric
EXPECT_EQ (nl.to_string (),
"circuit INV2LOAD (A=A,VSS=VSS,VDD=VDD);\n"
" device PMOS $1 (S=OUT1,G=A,D=VDD) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $2 (S=VDD,G=A,D=OUT1) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $3 (S=VSS,G=A,D=OUT1) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $4 (S=VSS,G=A,D=OUT1) (L=0.25,W=1.5,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $5 (S=OUT2,G=A,D=VDD) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $6 (S=VDD,G=A,D=OUT2) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $7 (S=OUT2,G=A,D=VSS) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $8 (S=OUT2,G=A,D=VSS) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $9 (S=OUT2,G=A,D=VDD) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device PMOS $10 (S=VDD,G=A,D=OUT2) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $11 (S=VSS,G=A,D=OUT2) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
" device NMOS $12 (S=OUT2,G=A,D=VSS) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n"
"end;\n"
)
}