From a47932a79e9671ad085a29df84386c45b4b399ef Mon Sep 17 00:00:00 2001 From: Matthias Koefferlein Date: Sat, 28 Mar 2020 09:49:41 +0100 Subject: [PATCH] Added one more testcase for join_symmetric_nets --- src/db/unit_tests/dbNetlistCompareTests.cc | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/db/unit_tests/dbNetlistCompareTests.cc b/src/db/unit_tests/dbNetlistCompareTests.cc index 6f0a259ed..c0d190f6d 100644 --- a/src/db/unit_tests/dbNetlistCompareTests.cc +++ b/src/db/unit_tests/dbNetlistCompareTests.cc @@ -3943,3 +3943,46 @@ TEST(28_NoSymmetryDetectionCases) } } +TEST(28_JoinSymmetricNets) +{ + const char *nls = + "circuit INV2LOAD (A=A,VSS=VSS,VDD=VDD);\n" + " device PMOS $1 (S=OUT1,G=A,D=VDD) (L=0.25,W=1);\n" + " device PMOS $2 (S=VDD,G=A,D=OUT1) (L=0.25,W=1);\n" + " device NMOS $3 (S=VSS,G=A,D=OUT1) (L=0.25,W=1);\n" + " device NMOS $4 (S=VSS,G=A,D=OUT1) (L=0.25,W=1.5);\n" + " device PMOS $5 (S=OUT2,G=A,D=VDD) (L=0.25,W=1);\n" + " device PMOS $6 (S=VDD,G=A,D=OUT2) (L=0.25,W=1);\n" + " device NMOS $7 (S=OUT2,G=A,D=VSS) (L=0.25,W=1);\n" + " device NMOS $8 (S=OUT2,G=A,D=VSS) (L=0.25,W=1);\n" + " device PMOS $9 (S=OUT3,G=A,D=VDD) (L=0.25,W=1);\n" + " device PMOS $10 (S=VDD,G=A,D=OUT3) (L=0.25,W=1);\n" + " device NMOS $11 (S=VSS,G=A,D=OUT3) (L=0.25,W=1);\n" + " device NMOS $12 (S=OUT3,G=A,D=VSS) (L=0.25,W=1);\n" + "end;\n"; + + db::Netlist nl; + prep_nl (nl, nls); + + db::NetlistComparer comp; + comp.join_symmetric_nets (nl.circuit_by_name ("INV2LOAD")); + + // NOTE $1 and $2 are joined because they are symmetric + EXPECT_EQ (nl.to_string (), + "circuit INV2LOAD (A=A,VSS=VSS,VDD=VDD);\n" + " device PMOS $1 (S=OUT1,G=A,D=VDD) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $2 (S=VDD,G=A,D=OUT1) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $3 (S=VSS,G=A,D=OUT1) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $4 (S=VSS,G=A,D=OUT1) (L=0.25,W=1.5,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $5 (S=OUT2,G=A,D=VDD) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $6 (S=VDD,G=A,D=OUT2) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $7 (S=OUT2,G=A,D=VSS) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $8 (S=OUT2,G=A,D=VSS) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $9 (S=OUT2,G=A,D=VDD) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device PMOS $10 (S=VDD,G=A,D=OUT2) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $11 (S=VSS,G=A,D=OUT2) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + " device NMOS $12 (S=OUT2,G=A,D=VSS) (L=0.25,W=1,AS=0,AD=0,PS=0,PD=0);\n" + "end;\n" + ) +} +