From a47190f3ab6c8d258122e4e67eed46f5edac7202 Mon Sep 17 00:00:00 2001
From: Matthias Koefferlein <matthias@koefferlein.de>
Date: Fri, 12 Jul 2019 17:43:43 +0200
Subject: [PATCH] Write short versions of LVS and L2N DB by default.

---
 src/drc/drc/built-in-macros/_drc_engine.rb    |    9 +-
 src/lvs/lvs/built-in-macros/_lvs_engine.rb    |   10 +-
 src/lvs/unit_tests/lvsBasicTests.cc           |    2 +-
 testdata/lvs/inv.lvs                          |    2 +-
 testdata/lvs/inv2.lvs                         |    2 +-
 testdata/lvs/inv2.lvsdb                       |  410 ++--
 testdata/lvs/ringo_simple.lvs                 |    2 +-
 testdata/lvs/ringo_simple_blackboxing.lvs     |    2 +-
 .../lvs/ringo_simple_implicit_connections.lvs |    2 +-
 testdata/lvs/ringo_simple_io.lvsdb            | 1766 ++++++++---------
 testdata/lvs/ringo_simple_io2.l2n             | 1048 +++++-----
 testdata/lvs/ringo_simple_io2.lvs             |    2 +-
 ...ngo_simple_net_and_circuit_equivalence.lvs |    2 +-
 testdata/lvs/ringo_simple_pin_swapping.lvs    |    2 +-
 .../lvs/ringo_simple_same_device_classes.lvs  |    2 +-
 testdata/lvs/ringo_simple_simplification.lvs  |    2 +-
 testdata/lvs/vexriscv.lvs                     |    2 +-
 17 files changed, 1550 insertions(+), 1717 deletions(-)

diff --git a/src/drc/drc/built-in-macros/_drc_engine.rb b/src/drc/drc/built-in-macros/_drc_engine.rb
index 099062b27..9801a9ae5 100644
--- a/src/drc/drc/built-in-macros/_drc_engine.rb
+++ b/src/drc/drc/built-in-macros/_drc_engine.rb
@@ -761,7 +761,7 @@ module DRC
     # %DRC%
     # @name report_netlist
     # @brief Specifies an extracted netlist report for output
-    # @synopsis report_netlist([ filename ])
+    # @synopsis report_netlist([ filename [, long ] ])
     # This method applies to runsets creating a netlist through
     # extraction. Extraction happens when connections and/or device
     # extractions are made. If this statement is used, the extracted
@@ -769,13 +769,16 @@ module DRC
     # layout-to-netlist report (L2N database) and shown in the 
     # netlist browser window. If a file name is given, the report
     # will also be written to the given file.
+    # If a file name is given and "long" is true, a verbose 
+    # version of the L2N DB format will be used.
     
-    def report_netlist(filename = nil)
+    def report_netlist(filename = nil, long = nil)
       @show_l2ndb = true
       if filename
         filename.is_a?(String) || raise("Argument must be string in report_netlist")
       end
       @output_l2ndb_file = filename
+      @output_l2ndb_long = long
     end
 
     # %DRC%
@@ -1415,7 +1418,7 @@ CODE
 
         l2ndb_file = _make_path(@output_l2ndb_file)
         info("Writing netlist database: #{l2ndb_file} ..")
-        @netter.l2n_data.write_l2n(l2ndb_file)
+        @netter.l2n_data.write_l2n(l2ndb_file, !@output_l2ndb_long)
 
       end
 
diff --git a/src/lvs/lvs/built-in-macros/_lvs_engine.rb b/src/lvs/lvs/built-in-macros/_lvs_engine.rb
index 9b900d245..89805d316 100644
--- a/src/lvs/lvs/built-in-macros/_lvs_engine.rb
+++ b/src/lvs/lvs/built-in-macros/_lvs_engine.rb
@@ -47,7 +47,7 @@ module LVS
 
         lvsdb_file = _make_path(@output_lvsdb_file)
         info("Writing LVS database: #{lvsdb_file} ..")
-        @netter.lvs_data.write(lvsdb_file)
+        @netter.lvs_data.write(lvsdb_file, !@output_lvsdb_long)
 
       end
 
@@ -56,11 +56,12 @@ module LVS
     # %LVS%
     # @name report_lvs
     # @brief Specifies an LVS report for output
-    # @synopsis report_lvs([ filename ])
+    # @synopsis report_lvs([ filename [, long ] ])
     # After the comparison step, the LVS database will be shown 
     # in the netlist database browser in a cross-reference view.
     # If a filename is given, the LVS database is also written to
-    # this file.
+    # this file. If a file name is given and "long" is true, a
+    # verbose version of the LVS DB format will be used.
     #
     # If this method is called together with report_netlist and two files each, two
     # files can be generated - one for the extracted netlist (L2N database) and one for the
@@ -70,12 +71,13 @@ module LVS
     # 
     # report_lvs is only effective if a comparison step is included.
     
-    def report_lvs(filename = nil)
+    def report_lvs(filename = nil, long = nil)
       @show_l2ndb = true
       if filename
         filename.is_a?(String) || raise("Argument must be string in report_lvs")
       end
       @output_lvsdb_file = filename
+      @output_lvsdb_long = long
     end
 
     # %LVS%
diff --git a/src/lvs/unit_tests/lvsBasicTests.cc b/src/lvs/unit_tests/lvsBasicTests.cc
index f87100265..528298111 100644
--- a/src/lvs/unit_tests/lvsBasicTests.cc
+++ b/src/lvs/unit_tests/lvsBasicTests.cc
@@ -47,7 +47,7 @@ TEST(1)
       "# Reports generated\n"
       "\n"
       "# LVS report to inv.lvsdb\n"
-      "report_lvs('%s')\n"
+      "report_lvs('%s', true)\n"
       "\n"
       "# Write extracted netlist to inv_extracted.cir\n"
       "target_netlist('%s', write_spice, 'Extracted by KLayout')\n"
diff --git a/testdata/lvs/inv.lvs b/testdata/lvs/inv.lvs
index 13de121de..96e8ab60b 100644
--- a/testdata/lvs/inv.lvs
+++ b/testdata/lvs/inv.lvs
@@ -6,7 +6,7 @@ deep
 # Reports generated
 
 # LVS report to inv.lvsdb
-report_lvs("inv.lvsdb")
+report_lvs("inv.lvsdb", true)
 
 # Write extracted netlist to inv_extracted.cir
 target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")
diff --git a/testdata/lvs/inv2.lvs b/testdata/lvs/inv2.lvs
index d8d372ae3..0c8806609 100644
--- a/testdata/lvs/inv2.lvs
+++ b/testdata/lvs/inv2.lvs
@@ -6,7 +6,7 @@ deep
 # Reports generated
 
 # LVS report to inv.lvsdb
-report_lvs("inv.lvsdb")
+report_lvs("inv.lvsdb", true)
 
 # Write extracted netlist to inv_extracted.cir
 target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")
diff --git a/testdata/lvs/inv2.lvsdb b/testdata/lvs/inv2.lvsdb
index deada80c9..568a79d1b 100644
--- a/testdata/lvs/inv2.lvsdb
+++ b/testdata/lvs/inv2.lvsdb
@@ -1,247 +1,201 @@
 #%lvsdb-klayout
-
-# Layout
-layout(
- top(INVERTER_WITH_DIODES)
- unit(0.001)
-
- # Layer section
- # This section lists the mask layers (drawing or derived) and their connections.
-
- # Mask layers
- layer(l3 'NWELL (1/0)')
- layer(l4 'POLY (5/0)')
- layer(l8 'CONTACT (6/0)')
- layer(l11 'METAL1 (7/0)')
- layer(l12 'METAL1_LABEL (7/1)')
- layer(l13 'VIA1 (8/0)')
- layer(l14 'METAL2 (9/0)')
- layer(l15 'METAL2_LABEL (9/1)')
- layer(l7)
- layer(l1)
- layer(l9)
- layer(l5)
- layer(l10)
-
- # Mask layer connectivity
- connect(l3 l3 l9)
- connect(l4 l4 l8)
- connect(l8 l4 l8 l11 l1 l9 l5 l10)
- connect(l11 l8 l11 l12 l13)
- connect(l12 l11 l12)
- connect(l13 l11 l13 l14)
- connect(l14 l13 l14 l15)
- connect(l15 l14 l15)
- connect(l7 l7)
- connect(l1 l8 l1)
- connect(l9 l3 l8 l9)
- connect(l5 l8 l5)
- connect(l10 l8 l10)
-
- # Global nets and connectivity
- global(l7 SUBSTRATE)
- global(l10 SUBSTRATE)
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Device abstracts section
- # Device abstracts list the pin shapes of the devices.
- device(D$PMOS PMOS
-  terminal(S
-   rect(l1 (-575 -750) (450 1500))
+J(
+ W(INVERTER_WITH_DIODES)
+ U(0.001)
+ L(l3 'NWELL (1/0)')
+ L(l4 'POLY (5/0)')
+ L(l8 'CONTACT (6/0)')
+ L(l11 'METAL1 (7/0)')
+ L(l12 'METAL1_LABEL (7/1)')
+ L(l13 'VIA1 (8/0)')
+ L(l14 'METAL2 (9/0)')
+ L(l15 'METAL2_LABEL (9/1)')
+ L(l7)
+ L(l1)
+ L(l9)
+ L(l5)
+ L(l10)
+ C(l3 l3 l9)
+ C(l4 l4 l8)
+ C(l8 l4 l8 l11 l1 l9 l5 l10)
+ C(l11 l8 l11 l12 l13)
+ C(l12 l11 l12)
+ C(l13 l11 l13 l14)
+ C(l14 l13 l14 l15)
+ C(l15 l14 l15)
+ C(l7 l7)
+ C(l1 l8 l1)
+ C(l9 l3 l8 l9)
+ C(l5 l8 l5)
+ C(l10 l8 l10)
+ G(l7 SUBSTRATE)
+ G(l10 SUBSTRATE)
+ D(D$PMOS PMOS
+  T(S
+   R(l1 (-575 -750) (450 1500))
   )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
+  T(G
+   R(l4 (-125 -750) (250 1500))
   )
-  terminal(D
-   rect(l1 (125 -750) (450 1500))
+  T(D
+   R(l1 (125 -750) (450 1500))
   )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
+  T(B
+   R(l3 (-125 -750) (250 1500))
   )
  )
- device(D$NMOS NMOS
-  terminal(S
-   rect(l5 (-575 -450) (450 900))
+ D(D$NMOS NMOS
+  T(S
+   R(l5 (-575 -450) (450 900))
   )
-  terminal(G
-   rect(l4 (-125 -450) (250 900))
+  T(G
+   R(l4 (-125 -450) (250 900))
   )
-  terminal(D
-   rect(l5 (125 -450) (450 900))
+  T(D
+   R(l5 (125 -450) (450 900))
   )
-  terminal(B
-   rect(l7 (-125 -450) (250 900))
+  T(B
+   R(l7 (-125 -450) (250 900))
   )
  )
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(INVERTER_WITH_DIODES
-
-  # Circuit boundary
-  rect((0 0) (3000 6150))
-
-  # Nets with their geometries
-  net(1 name(IN)
-   rect(l4 (900 50) (250 1050))
-   rect(l4 (-250 0) (250 3100))
-   rect(l4 (-250 0) (250 1650))
-   rect(l4 (-800 -3100) (550 400))
-   rect(l8 (-450 -300) (200 200))
-   rect(l11 (-300 -300) (400 400))
-   rect(l12 (-201 -201) (2 2))
+ X(INVERTER_WITH_DIODES
+  R((0 0) (3000 6150))
+  N(1 I(IN)
+   R(l4 (900 50) (250 1050))
+   R(l4 (-250 0) (250 3100))
+   R(l4 (-250 0) (250 1650))
+   R(l4 (-800 -3100) (550 400))
+   R(l8 (-450 -300) (200 200))
+   R(l11 (-300 -300) (400 400))
+   R(l12 (-201 -201) (2 2))
   )
-  net(2 name(VDD)
-   rect(l3 (0 2950) (3000 3200))
-   rect(l8 (-2450 -1800) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l8 (1400 -800) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l11 (-1850 -1200) (300 1600))
-   rect(l11 (1300 -1200) (300 1200))
-   rect(l13 (-1850 -800) (200 200))
-   rect(l13 (-200 300) (200 200))
-   rect(l13 (1400 -700) (200 200))
-   rect(l13 (-200 300) (200 200))
-   rect(l14 (-2350 -850) (3000 1000))
-   rect(l15 (-151 -851) (2 2))
-   rect(l1 (-2401 -851) (450 1500))
-   rect(l9 (1050 -1200) (600 1200))
+  N(2 I(VDD)
+   R(l3 (0 2950) (3000 3200))
+   R(l8 (-2450 -1800) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l8 (1400 -800) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l11 (-1850 -1200) (300 1600))
+   R(l11 (1300 -1200) (300 1200))
+   R(l13 (-1850 -800) (200 200))
+   R(l13 (-200 300) (200 200))
+   R(l13 (1400 -700) (200 200))
+   R(l13 (-200 300) (200 200))
+   R(l14 (-2350 -850) (3000 1000))
+   R(l15 (-151 -851) (2 2))
+   R(l1 (-2401 -851) (450 1500))
+   R(l9 (1050 -1200) (600 1200))
   )
-  net(3 name(OUT)
-   rect(l8 (1300 4350) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l8 (-200 -5250) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l11 (-250 3250) (300 1400))
-   rect(l11 (-300 -4600) (300 3200))
-   rect(l11 (-300 -2900) (450 400))
-   rect(l11 (-450 -1550) (300 850))
-   rect(l12 (-51 499) (2 2))
-   rect(l1 (-351 2649) (450 1500))
-   rect(l5 (-450 -5500) (450 900))
+  N(3 I(OUT)
+   R(l8 (1300 4350) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l8 (-200 -5250) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l11 (-250 3250) (300 1400))
+   R(l11 (-300 -4600) (300 3200))
+   R(l11 (-300 -2900) (450 400))
+   R(l11 (-450 -1550) (300 850))
+   R(l12 (-51 499) (2 2))
+   R(l1 (-351 2649) (450 1500))
+   R(l5 (-450 -5500) (450 900))
   )
-  net(4 name(VSS)
-   rect(l8 (550 300) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l8 (1400 -550) (200 200))
-   rect(l8 (-200 300) (200 200))
-   rect(l11 (-1850 -1100) (300 1050))
-   rect(l11 (1300 -1050) (300 1200))
-   rect(l13 (-1850 -1100) (200 200))
-   rect(l13 (-200 300) (200 200))
-   rect(l13 (1400 -700) (200 200))
-   rect(l13 (-200 300) (200 200))
-   rect(l14 (-2350 -850) (3000 1000))
-   rect(l15 (-151 -851) (2 2))
-   rect(l5 (-2401 49) (450 900))
-   rect(l10 (1050 -900) (600 1200))
+  N(4 I(VSS)
+   R(l8 (550 300) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l8 (1400 -550) (200 200))
+   R(l8 (-200 300) (200 200))
+   R(l11 (-1850 -1100) (300 1050))
+   R(l11 (1300 -1050) (300 1200))
+   R(l13 (-1850 -1100) (200 200))
+   R(l13 (-200 300) (200 200))
+   R(l13 (1400 -700) (200 200))
+   R(l13 (-200 300) (200 200))
+   R(l14 (-2350 -850) (3000 1000))
+   R(l15 (-151 -851) (2 2))
+   R(l5 (-2401 49) (450 900))
+   R(l10 (1050 -900) (600 1200))
   )
-
-  # Devices and their connections
-  device(1 D$PMOS
-   location(1025 4950)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.675)
-   param(AD 0.675)
-   param(PS 3.9)
-   param(PD 3.9)
-   terminal(S 2)
-   terminal(G 1)
-   terminal(D 3)
-   terminal(B 2)
+  D(1 D$PMOS
+   Y(1025 4950)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0.675)
+   E(AD 0.675)
+   E(PS 3.9)
+   E(PD 3.9)
+   T(S 2)
+   T(G 1)
+   T(D 3)
+   T(B 2)
   )
-  device(2 D$NMOS
-   location(1025 650)
-   param(L 0.25)
-   param(W 0.9)
-   param(AS 0.405)
-   param(AD 0.405)
-   param(PS 2.7)
-   param(PD 2.7)
-   terminal(S 4)
-   terminal(G 1)
-   terminal(D 3)
-   terminal(B 4)
-  )
-
- )
-)
-
-# Reference netlist
-reference(
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(INVERTER_WITH_DIODES
-
-  # Nets
-  net(1 name(VSS))
-  net(2 name(IN))
-  net(3 name(OUT))
-  net(4 name(VDD))
-
-  # Outgoing pins and their connections to nets
-  pin(1)
-  pin(2)
-  pin(3)
-  pin(4)
-
-  # Devices and their connections
-  device(1 PMOS
-   name(P)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 4)
-   terminal(G 2)
-   terminal(D 3)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name(N)
-   param(L 0.25)
-   param(W 0.9)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 2)
-   terminal(D 1)
-   terminal(B 1)
-  )
-
- )
-)
-
-# Cross reference
-xref(
- circuit(INVERTER_WITH_DIODES INVERTER_WITH_DIODES match
-  xref(
-   net(1 2 match)
-   net(3 3 match)
-   net(2 4 match)
-   net(4 1 match)
-   pin(() 0 match)
-   pin(() 1 match)
-   pin(() 2 match)
-   pin(() 3 match)
-   device(2 2 match)
-   device(1 1 match)
+  D(2 D$NMOS
+   Y(1025 650)
+   E(L 0.25)
+   E(W 0.9)
+   E(AS 0.405)
+   E(AD 0.405)
+   E(PS 2.7)
+   E(PD 2.7)
+   T(S 4)
+   T(G 1)
+   T(D 3)
+   T(B 4)
+  )
+ )
+)
+H(
+ X(INVERTER_WITH_DIODES
+  N(1 I(VSS))
+  N(2 I(IN))
+  N(3 I(OUT))
+  N(4 I(VDD))
+  P(1)
+  P(2)
+  P(3)
+  P(4)
+  D(1 PMOS
+   I(P)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 4)
+   T(G 2)
+   T(D 3)
+   T(B 4)
+  )
+  D(2 NMOS
+   I(N)
+   E(L 0.25)
+   E(W 0.9)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 3)
+   T(G 2)
+   T(D 1)
+   T(B 1)
+  )
+ )
+)
+Z(
+ X(INVERTER_WITH_DIODES INVERTER_WITH_DIODES 1
+  Z(
+   N(1 2 1)
+   N(3 3 1)
+   N(2 4 1)
+   N(4 1 1)
+   P(() 0 1)
+   P(() 1 1)
+   P(() 2 1)
+   P(() 3 1)
+   D(2 2 1)
+   D(1 1 1)
   )
  )
 )
diff --git a/testdata/lvs/ringo_simple.lvs b/testdata/lvs/ringo_simple.lvs
index c96269116..057f39c25 100644
--- a/testdata/lvs/ringo_simple.lvs
+++ b/testdata/lvs/ringo_simple.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "RINGO")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 
 target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
 
diff --git a/testdata/lvs/ringo_simple_blackboxing.lvs b/testdata/lvs/ringo_simple_blackboxing.lvs
index 97c56546f..475262be3 100644
--- a/testdata/lvs/ringo_simple_blackboxing.lvs
+++ b/testdata/lvs/ringo_simple_blackboxing.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "RINGO")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 
 target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
 
diff --git a/testdata/lvs/ringo_simple_implicit_connections.lvs b/testdata/lvs/ringo_simple_implicit_connections.lvs
index 43d4b7e7c..056cf97d8 100644
--- a/testdata/lvs/ringo_simple_implicit_connections.lvs
+++ b/testdata/lvs/ringo_simple_implicit_connections.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "RINGO")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 
 target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
 
diff --git a/testdata/lvs/ringo_simple_io.lvsdb b/testdata/lvs/ringo_simple_io.lvsdb
index 5e05088fb..9d2257420 100644
--- a/testdata/lvs/ringo_simple_io.lvsdb
+++ b/testdata/lvs/ringo_simple_io.lvsdb
@@ -1,971 +1,891 @@
 #%lvsdb-klayout
-
-# Layout
-layout(
- top(RINGO)
- unit(0.001)
-
- # Layer section
- # This section lists the mask layers (drawing or derived) and their connections.
-
- # Mask layers
- layer(l3 '1/0')
- layer(l4 '5/0')
- layer(l8 '8/0')
- layer(l11 '9/0')
- layer(l12 '10/0')
- layer(l13 '11/0')
- layer(l7)
- layer(l1)
- layer(l9)
- layer(l5)
- layer(l10)
-
- # Mask layer connectivity
- connect(l3 l3 l9)
- connect(l4 l4 l8)
- connect(l8 l4 l8 l11 l1 l9 l5 l10)
- connect(l11 l8 l11 l12)
- connect(l12 l11 l12 l13)
- connect(l13 l12 l13)
- connect(l7 l7)
- connect(l1 l8 l1)
- connect(l9 l3 l8 l9)
- connect(l5 l8 l5)
- connect(l10 l8 l10)
-
- # Global nets and connectivity
- global(l7 SUBSTRATE)
- global(l10 SUBSTRATE)
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Device abstracts section
- # Device abstracts list the pin shapes of the devices.
- device(D$PMOS PMOS
-  terminal(S
-   rect(l1 (-550 -750) (425 1500))
+J(
+ W(RINGO)
+ U(0.001)
+ L(l3 '1/0')
+ L(l4 '5/0')
+ L(l8 '8/0')
+ L(l11 '9/0')
+ L(l12 '10/0')
+ L(l13 '11/0')
+ L(l7)
+ L(l1)
+ L(l9)
+ L(l5)
+ L(l10)
+ C(l3 l3 l9)
+ C(l4 l4 l8)
+ C(l8 l4 l8 l11 l1 l9 l5 l10)
+ C(l11 l8 l11 l12)
+ C(l12 l11 l12 l13)
+ C(l13 l12 l13)
+ C(l7 l7)
+ C(l1 l8 l1)
+ C(l9 l3 l8 l9)
+ C(l5 l8 l5)
+ C(l10 l8 l10)
+ G(l7 SUBSTRATE)
+ G(l10 SUBSTRATE)
+ D(D$PMOS PMOS
+  T(S
+   R(l1 (-550 -750) (425 1500))
   )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
+  T(G
+   R(l4 (-125 -750) (250 1500))
   )
-  terminal(D
-   rect(l1 (125 -750) (450 1500))
+  T(D
+   R(l1 (125 -750) (450 1500))
   )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
+  T(B
+   R(l3 (-125 -750) (250 1500))
   )
  )
- device(D$PMOS$1 PMOS
-  terminal(S
-   rect(l1 (-575 -750) (450 1500))
+ D(D$PMOS$1 PMOS
+  T(S
+   R(l1 (-575 -750) (450 1500))
   )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
+  T(G
+   R(l4 (-125 -750) (250 1500))
   )
-  terminal(D
-   rect(l1 (125 -750) (425 1500))
+  T(D
+   R(l1 (125 -750) (425 1500))
   )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
+  T(B
+   R(l3 (-125 -750) (250 1500))
   )
  )
- device(D$PMOS$2 PMOS
-  terminal(S
-   rect(l1 (-550 -750) (425 1500))
+ D(D$PMOS$2 PMOS
+  T(S
+   R(l1 (-550 -750) (425 1500))
   )
-  terminal(G
-   rect(l4 (-125 -750) (250 1500))
+  T(G
+   R(l4 (-125 -750) (250 1500))
   )
-  terminal(D
-   rect(l1 (125 -750) (425 1500))
+  T(D
+   R(l1 (125 -750) (425 1500))
   )
-  terminal(B
-   rect(l3 (-125 -750) (250 1500))
+  T(B
+   R(l3 (-125 -750) (250 1500))
   )
  )
- device(D$NMOS NMOS
-  terminal(S
-   rect(l5 (-550 -475) (425 950))
+ D(D$NMOS NMOS
+  T(S
+   R(l5 (-550 -475) (425 950))
   )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
+  T(G
+   R(l4 (-125 -475) (250 950))
   )
-  terminal(D
-   rect(l5 (125 -475) (450 950))
+  T(D
+   R(l5 (125 -475) (450 950))
   )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
+  T(B
+   R(l7 (-125 -475) (250 950))
   )
  )
- device(D$NMOS$1 NMOS
-  terminal(S
-   rect(l5 (-575 -475) (450 950))
+ D(D$NMOS$1 NMOS
+  T(S
+   R(l5 (-575 -475) (450 950))
   )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
+  T(G
+   R(l4 (-125 -475) (250 950))
   )
-  terminal(D
-   rect(l5 (125 -475) (425 950))
+  T(D
+   R(l5 (125 -475) (425 950))
   )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
+  T(B
+   R(l7 (-125 -475) (250 950))
   )
  )
- device(D$NMOS$2 NMOS
-  terminal(S
-   rect(l5 (-550 -475) (425 950))
+ D(D$NMOS$2 NMOS
+  T(S
+   R(l5 (-550 -475) (425 950))
   )
-  terminal(G
-   rect(l4 (-125 -475) (250 950))
+  T(G
+   R(l4 (-125 -475) (250 950))
   )
-  terminal(D
-   rect(l5 (125 -475) (425 950))
+  T(D
+   R(l5 (125 -475) (425 950))
   )
-  terminal(B
-   rect(l7 (-125 -475) (250 950))
+  T(B
+   R(l7 (-125 -475) (250 950))
   )
  )
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Circuit boundary
-  rect((-100 400) (2600 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -790) (300 1700))
-   rect(l11 (-1350 0) (2400 800))
-   rect(l11 (-1151 -401) (2 2))
-   rect(l1 (-276 -2151) (425 1500))
-   rect(l1 (-400 -1500) (425 1500))
+ X(ND2X1
+  R((-100 400) (2600 7600))
+  N(1 I(VDD)
+   R(l8 (1110 5160) (180 180))
+   R(l8 (-180 920) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l11 (-240 -790) (300 1700))
+   R(l11 (-1350 0) (2400 800))
+   R(l11 (-1151 -401) (2 2))
+   R(l1 (-276 -2151) (425 1500))
+   R(l1 (-400 -1500) (425 1500))
   )
-  net(2 name(OUT)
-   rect(l8 (1810 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-1580 3760) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (1220 920) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
-   rect(l11 (-110 1390) (300 1400))
-   polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
-   rect(l11 (-141 -501) (2 2))
-   rect(l11 (-1751 1099) (300 1400))
-   rect(l11 (1100 -1700) (300 300))
-   rect(l11 (-300 0) (300 1400))
-   rect(l1 (-1750 -1450) (425 1500))
-   rect(l1 (950 -1500) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
+  N(2 I(OUT)
+   R(l8 (1810 1770) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (-1580 3760) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (1220 920) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (-180 370) (180 180))
+   Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+   R(l11 (-110 1390) (300 1400))
+   Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+   R(l11 (-141 -501) (2 2))
+   R(l11 (-1751 1099) (300 1400))
+   R(l11 (1100 -1700) (300 300))
+   R(l11 (-300 0) (300 1400))
+   R(l1 (-1750 -1450) (425 1500))
+   R(l1 (950 -1500) (425 1500))
+   R(l5 (-425 -4890) (425 950))
   )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (2400 800))
-   rect(l11 (-1151 -401) (2 2))
-   rect(l5 (-951 859) (425 950))
+  N(3 I(VSS)
+   R(l8 (410 1770) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-240 -1300) (300 1360))
+   R(l11 (-650 -2160) (2400 800))
+   R(l11 (-1151 -401) (2 2))
+   R(l5 (-951 859) (425 950))
   )
-  net(4
-   rect(l3 (-100 4500) (2600 3500))
+  N(4
+   R(l3 (-100 4500) (2600 3500))
   )
-  net(5 name(B)
-   rect(l4 (1425 2860) (250 1940))
-   rect(l4 (-345 -950) (300 300))
-   rect(l4 (-205 650) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-285 1050) (180 180))
-   rect(l11 (-71 -91) (2 2))
-   rect(l11 (-171 -151) (300 300))
+  N(5 I(B)
+   R(l4 (1425 2860) (250 1940))
+   R(l4 (-345 -950) (300 300))
+   R(l4 (-205 650) (250 2000))
+   R(l4 (-250 -2000) (250 2000))
+   R(l4 (-250 -5390) (250 1450))
+   R(l8 (-285 1050) (180 180))
+   R(l11 (-71 -91) (2 2))
+   R(l11 (-171 -151) (300 300))
   )
-  net(6 name(A)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-325 -1850) (300 300))
-   rect(l4 (-225 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-265 150) (180 180))
-   rect(l11 (-91 -91) (2 2))
-   rect(l11 (-151 -151) (300 300))
+  N(6 I(A)
+   R(l4 (725 2860) (250 1940))
+   R(l4 (-325 -1850) (300 300))
+   R(l4 (-225 1550) (250 2000))
+   R(l4 (-250 -2000) (250 2000))
+   R(l4 (-250 -5390) (250 1450))
+   R(l8 (-265 150) (180 180))
+   R(l11 (-91 -91) (2 2))
+   R(l11 (-151 -151) (300 300))
   )
-  net(7 name(SUBSTRATE))
-  net(8
-   rect(l5 (975 1660) (425 950))
-   rect(l5 (-400 -950) (425 950))
+  N(7 I(SUBSTRATE))
+  N(8
+   R(l5 (975 1660) (425 950))
+   R(l5 (-400 -950) (425 950))
   )
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(B))
-  pin(6 name(A))
-  pin(7 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.3375)
-   param(PS 3.85)
-   param(PD 1.95)
-   terminal(S 2)
-   terminal(G 6)
-   terminal(D 1)
-   terminal(B 4)
+  P(1 I(VDD))
+  P(2 I(OUT))
+  P(3 I(VSS))
+  P(4)
+  P(5 I(B))
+  P(6 I(A))
+  P(7 I(SUBSTRATE))
+  D(1 D$PMOS
+   Y(850 5800)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0.6375)
+   E(AD 0.3375)
+   E(PS 3.85)
+   E(PD 1.95)
+   T(S 2)
+   T(G 6)
+   T(D 1)
+   T(B 4)
   )
-  device(2 D$PMOS$1
-   location(1550 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.3375)
-   param(AD 0.6375)
-   param(PS 1.95)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
+  D(2 D$PMOS$1
+   Y(1550 5800)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0.3375)
+   E(AD 0.6375)
+   E(PS 1.95)
+   E(PD 3.85)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
   )
-  device(3 D$NMOS
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.21375)
-   param(PS 2.75)
-   param(PD 1.4)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
+  D(3 D$NMOS
+   Y(850 2135)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.40375)
+   E(AD 0.21375)
+   E(PS 2.75)
+   E(PD 1.4)
+   T(S 3)
+   T(G 6)
+   T(D 8)
+   T(B 7)
   )
-  device(4 D$NMOS$1
-   location(1550 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.21375)
-   param(AD 0.40375)
-   param(PS 1.4)
-   param(PD 2.75)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
-
- )
- circuit(INVX1
-
-  # Circuit boundary
-  rect((-100 400) (2000 7600))
-
-  # Nets with their geometries
-  net(1 name(VDD)
-   rect(l8 (410 6260) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l11 (-240 -240) (300 1400))
-   rect(l11 (-650 300) (1800 800))
-   rect(l11 (-1450 -1100) (300 300))
-   rect(l11 (299 399) (2 2))
-   rect(l1 (-651 -2151) (425 1500))
-  )
-  net(2 name(OUT)
-   rect(l8 (1110 5160) (180 180))
-   rect(l8 (-180 920) (180 180))
-   rect(l8 (-180 -730) (180 180))
-   rect(l8 (-180 -4120) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -790) (300 4790))
-   rect(l11 (-151 -2501) (2 2))
-   rect(l1 (-226 1049) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(3 name(VSS)
-   rect(l8 (410 1770) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-240 -1300) (300 1360))
-   rect(l11 (-650 -2160) (1800 800))
-   rect(l11 (-851 -401) (2 2))
-   rect(l5 (-651 859) (425 950))
-  )
-  net(4
-   rect(l3 (-100 4500) (2000 3500))
-  )
-  net(5 name(IN)
-   rect(l4 (725 2860) (250 1940))
-   rect(l4 (-525 -1850) (300 300))
-   rect(l4 (-25 1550) (250 2000))
-   rect(l4 (-250 -2000) (250 2000))
-   rect(l4 (-250 -5390) (250 1450))
-   rect(l8 (-465 150) (180 180))
-   rect(l11 (-91 -91) (2 2))
-   rect(l11 (-151 -151) (300 300))
-  )
-  net(6 name(SUBSTRATE))
-
-  # Outgoing pins and their connections to nets
-  pin(1 name(VDD))
-  pin(2 name(OUT))
-  pin(3 name(VSS))
-  pin(4)
-  pin(5 name(IN))
-  pin(6 name(SUBSTRATE))
-
-  # Devices and their connections
-  device(1 D$PMOS$2
-   location(850 5800)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0.6375)
-   param(AD 0.6375)
-   param(PS 3.85)
-   param(PD 3.85)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 D$NMOS$2
-   location(850 2135)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0.40375)
-   param(AD 0.40375)
-   param(PS 2.75)
-   param(PD 2.75)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Circuit boundary
-  rect((0 350) (25800 7650))
-
-  # Nets with their geometries
-  net(1
-   rect(l8 (4710 3010) (180 180))
-   rect(l11 (-850 -240) (610 300))
-   rect(l1 (-2550 1800) (425 1500))
-   rect(l1 (950 -1500) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(2
-   rect(l8 (6510 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(3
-   rect(l8 (8310 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(4
-   rect(l8 (10110 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(5
-   rect(l8 (11910 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(6
-   rect(l8 (13710 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(7
-   rect(l8 (15510 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(8
-   rect(l8 (17310 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(9
-   rect(l8 (19110 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(10
-   rect(l8 (20910 3010) (180 180))
-   rect(l11 (-1140 -240) (900 300))
-   rect(l1 (-1275 1800) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(11 name(FB)
-   rect(l8 (22710 3010) (180 180))
-   rect(l8 (-19700 720) (180 180))
-   rect(l11 (18380 -1140) (900 300))
-   rect(l11 (-19530 590) (320 320))
-   rect(l11 (17820 -320) (320 320))
-   rect(l12 (-18400 -260) (200 200))
-   rect(l12 (17940 -200) (200 200))
-   rect(l13 (-18040 -300) (17740 400))
-   rect(l13 (-17921 -201) (2 2))
-   rect(l13 (-221 -201) (400 400))
-   rect(l13 (17740 -400) (400 400))
-   rect(l1 (-245 850) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(12 name(VDD)
-   rect(l3 (500 4500) (1400 3500))
-   rect(l3 (-1900 -3500) (600 3500))
-   rect(l3 (23300 -3500) (1400 3500))
-   rect(l3 (-100 -3500) (600 3500))
-   rect(l8 (-24690 -1240) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (23220 370) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l11 (-21741 859) (2 2))
-   rect(l11 (-2351 -451) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-101 -351) (2 2))
-   rect(l11 (-1251 -401) (600 800))
-   rect(l11 (23400 -800) (1200 800))
-   rect(l11 (-750 -1450) (300 1400))
-   rect(l11 (-101 -351) (2 2))
-   rect(l11 (549 -401) (600 800))
-   rect(l1 (-23025 -2550) (425 1500))
-   rect(l1 (-400 -1500) (425 1500))
-   rect(l1 (1275 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l1 (1375 -1500) (425 1500))
-   rect(l9 (-21975 -450) (500 1500))
-   rect(l9 (22900 -1500) (500 1500))
-  )
-  net(13 name(OUT)
-   rect(l11 (23440 3840) (320 320))
-   rect(l12 (-260 -260) (200 200))
-   rect(l13 (-101 -101) (2 2))
-   rect(l13 (-201 -201) (400 400))
-   rect(l1 (-625 850) (425 1500))
-   rect(l5 (-425 -4890) (425 950))
-  )
-  net(14 name(ENABLE)
-   rect(l8 (2510 3010) (180 180))
-   rect(l11 (-250 -250) (320 320))
-   rect(l12 (-260 -260) (200 200))
-   rect(l13 (-101 -101) (2 2))
-   rect(l13 (-201 -201) (400 400))
-  )
-  net(15 name(VSS)
-   rect(l8 (1110 1610) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l8 (23220 370) (180 180))
-   rect(l8 (-180 -1280) (180 180))
-   rect(l8 (-180 370) (180 180))
-   rect(l11 (-21741 -391) (2 2))
-   rect(l11 (-1901 -401) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-551 -401) (2 2))
-   rect(l11 (-1251 -401) (600 800))
-   rect(l11 (23850 -750) (300 1400))
-   rect(l11 (-750 -1450) (1200 800))
-   rect(l11 (-551 -401) (2 2))
-   rect(l11 (549 -401) (600 800))
-   rect(l5 (-23700 460) (425 950))
-   rect(l5 (1975 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l5 (1375 -950) (425 950))
-   rect(l10 (-21975 -2210) (500 1500))
-   rect(l10 (22900 -1500) (500 1500))
-  )
-
-  # Outgoing pins and their connections to nets
-  pin(11 name(FB))
-  pin(12 name(VDD))
-  pin(13 name(OUT))
-  pin(14 name(ENABLE))
-  pin(15 name(VSS))
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 location(1800 0)
-   pin(0 12)
-   pin(1 1)
-   pin(2 15)
-   pin(3 12)
-   pin(4 11)
-   pin(5 14)
-   pin(6 15)
-  )
-  circuit(2 INVX1 location(4200 0)
-   pin(0 12)
-   pin(1 2)
-   pin(2 15)
-   pin(3 12)
-   pin(4 1)
-   pin(5 15)
-  )
-  circuit(3 INVX1 location(6000 0)
-   pin(0 12)
-   pin(1 3)
-   pin(2 15)
-   pin(3 12)
-   pin(4 2)
-   pin(5 15)
-  )
-  circuit(4 INVX1 location(7800 0)
-   pin(0 12)
-   pin(1 4)
-   pin(2 15)
-   pin(3 12)
-   pin(4 3)
-   pin(5 15)
-  )
-  circuit(5 INVX1 location(9600 0)
-   pin(0 12)
-   pin(1 5)
-   pin(2 15)
-   pin(3 12)
-   pin(4 4)
-   pin(5 15)
-  )
-  circuit(6 INVX1 location(11400 0)
-   pin(0 12)
-   pin(1 6)
-   pin(2 15)
-   pin(3 12)
-   pin(4 5)
-   pin(5 15)
-  )
-  circuit(7 INVX1 location(13200 0)
-   pin(0 12)
-   pin(1 7)
-   pin(2 15)
-   pin(3 12)
-   pin(4 6)
-   pin(5 15)
-  )
-  circuit(8 INVX1 location(15000 0)
-   pin(0 12)
-   pin(1 8)
-   pin(2 15)
-   pin(3 12)
-   pin(4 7)
-   pin(5 15)
-  )
-  circuit(9 INVX1 location(16800 0)
-   pin(0 12)
-   pin(1 9)
-   pin(2 15)
-   pin(3 12)
-   pin(4 8)
-   pin(5 15)
-  )
-  circuit(10 INVX1 location(18600 0)
-   pin(0 12)
-   pin(1 10)
-   pin(2 15)
-   pin(3 12)
-   pin(4 9)
-   pin(5 15)
-  )
-  circuit(11 INVX1 location(20400 0)
-   pin(0 12)
-   pin(1 11)
-   pin(2 15)
-   pin(3 12)
-   pin(4 10)
-   pin(5 15)
-  )
-  circuit(12 INVX1 location(22200 0)
-   pin(0 12)
-   pin(1 13)
-   pin(2 15)
-   pin(3 12)
-   pin(4 11)
-   pin(5 15)
-  )
-
- )
-)
-
-# Reference netlist
-reference(
-
- # Device class section
- class(PMOS MOS4)
- class(NMOS MOS4)
-
- # Circuit section
- # Circuits are the hierarchical building blocks of the netlist.
- circuit(ND2X1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(B))
-  net(6 name(A))
-  net(7 name(BULK))
-  net(8 name('1'))
-
-  # Outgoing pins and their connections to nets
-  pin(1)
-  pin(2)
-  pin(3)
-  pin(4)
-  pin(5)
-  pin(6)
-  pin(7)
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 2)
-   terminal(G 6)
-   terminal(D 1)
-   terminal(B 4)
-  )
-  device(2 PMOS
-   name($2)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(3 NMOS
-   name($3)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 6)
-   terminal(D 8)
-   terminal(B 7)
-  )
-  device(4 NMOS
-   name($4)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 8)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 7)
-  )
-
- )
- circuit(INVX1
-
-  # Nets
-  net(1 name(VDD))
-  net(2 name(OUT))
-  net(3 name(VSS))
-  net(4 name(NWELL))
-  net(5 name(IN))
-  net(6 name(BULK))
-
-  # Outgoing pins and their connections to nets
-  pin(1)
-  pin(2)
-  pin(3)
-  pin(4)
-  pin(5)
-  pin(6)
-
-  # Devices and their connections
-  device(1 PMOS
-   name($1)
-   param(L 0.25)
-   param(W 1.5)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 1)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 4)
-  )
-  device(2 NMOS
-   name($2)
-   param(L 0.25)
-   param(W 0.95)
-   param(AS 0)
-   param(AD 0)
-   param(PS 0)
-   param(PD 0)
-   terminal(S 3)
-   terminal(G 5)
-   terminal(D 2)
-   terminal(B 6)
-  )
-
- )
- circuit(RINGO
-
-  # Nets
-  net(1 name(VSS))
-  net(2 name(VDD))
-  net(3 name(FB))
-  net(4 name(ENABLE))
-  net(5 name(OUT))
-  net(6 name('1'))
-  net(7 name('2'))
-  net(8 name('3'))
-  net(9 name('4'))
-  net(10 name('5'))
-  net(11 name('6'))
-  net(12 name('7'))
-  net(13 name('8'))
-  net(14 name('9'))
-  net(15 name('10'))
-
-  # Outgoing pins and their connections to nets
-  pin(1)
-  pin(2)
-  pin(3)
-  pin(4)
-  pin(5)
-
-  # Subcircuits and their connections
-  circuit(1 ND2X1 name($1)
-   pin(0 2)
-   pin(1 6)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 4)
-   pin(6 1)
-  )
-  circuit(2 INVX1 name($2)
-   pin(0 2)
-   pin(1 7)
-   pin(2 1)
-   pin(3 2)
-   pin(4 6)
-   pin(5 1)
-  )
-  circuit(3 INVX1 name($3)
-   pin(0 2)
-   pin(1 8)
-   pin(2 1)
-   pin(3 2)
-   pin(4 7)
-   pin(5 1)
-  )
-  circuit(4 INVX1 name($4)
-   pin(0 2)
-   pin(1 9)
-   pin(2 1)
-   pin(3 2)
-   pin(4 8)
-   pin(5 1)
-  )
-  circuit(5 INVX1 name($5)
-   pin(0 2)
-   pin(1 10)
-   pin(2 1)
-   pin(3 2)
-   pin(4 9)
-   pin(5 1)
-  )
-  circuit(6 INVX1 name($6)
-   pin(0 2)
-   pin(1 11)
-   pin(2 1)
-   pin(3 2)
-   pin(4 10)
-   pin(5 1)
-  )
-  circuit(7 INVX1 name($7)
-   pin(0 2)
-   pin(1 12)
-   pin(2 1)
-   pin(3 2)
-   pin(4 11)
-   pin(5 1)
-  )
-  circuit(8 INVX1 name($8)
-   pin(0 2)
-   pin(1 13)
-   pin(2 1)
-   pin(3 2)
-   pin(4 12)
-   pin(5 1)
-  )
-  circuit(9 INVX1 name($9)
-   pin(0 2)
-   pin(1 14)
-   pin(2 1)
-   pin(3 2)
-   pin(4 13)
-   pin(5 1)
-  )
-  circuit(10 INVX1 name($10)
-   pin(0 2)
-   pin(1 15)
-   pin(2 1)
-   pin(3 2)
-   pin(4 14)
-   pin(5 1)
-  )
-  circuit(11 INVX1 name($11)
-   pin(0 2)
-   pin(1 3)
-   pin(2 1)
-   pin(3 2)
-   pin(4 15)
-   pin(5 1)
-  )
-  circuit(12 INVX1 name($12)
-   pin(0 2)
-   pin(1 5)
-   pin(2 1)
-   pin(3 2)
-   pin(4 3)
-   pin(5 1)
-  )
-
- )
-)
-
-# Cross reference
-xref(
- circuit(INVX1 INVX1 match
-  xref(
-   net(4 4 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(6 6 match)
-   net(1 1 match)
-   net(3 3 match)
-   pin(3 3 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(5 5 match)
-   pin(0 0 match)
-   pin(2 2 match)
-   device(1 1 match)
-   device(2 2 match)
+  D(4 D$NMOS$1
+   Y(1550 2135)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.21375)
+   E(AD 0.40375)
+   E(PS 1.4)
+   E(PD 2.75)
+   T(S 8)
+   T(G 5)
+   T(D 2)
+   T(B 7)
   )
  )
- circuit(ND2X1 ND2X1 match
-  xref(
-   net(8 8 match)
-   net(4 4 match)
-   net(6 6 match)
-   net(5 5 match)
-   net(2 2 match)
-   net(7 7 match)
-   net(1 1 match)
-   net(3 3 match)
-   pin(3 3 match)
-   pin(5 5 match)
-   pin(4 4 match)
-   pin(1 1 match)
-   pin(6 6 match)
-   pin(0 0 match)
-   pin(2 2 match)
-   device(1 1 match)
-   device(2 2 match)
-   device(3 3 match)
-   device(4 4 match)
+ X(INVX1
+  R((-100 400) (2000 7600))
+  N(1 I(VDD)
+   R(l8 (410 6260) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l11 (-240 -240) (300 1400))
+   R(l11 (-650 300) (1800 800))
+   R(l11 (-1450 -1100) (300 300))
+   R(l11 (299 399) (2 2))
+   R(l1 (-651 -2151) (425 1500))
+  )
+  N(2 I(OUT)
+   R(l8 (1110 5160) (180 180))
+   R(l8 (-180 920) (180 180))
+   R(l8 (-180 -730) (180 180))
+   R(l8 (-180 -4120) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-240 -790) (300 4790))
+   R(l11 (-151 -2501) (2 2))
+   R(l1 (-226 1049) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(3 I(VSS)
+   R(l8 (410 1770) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-240 -1300) (300 1360))
+   R(l11 (-650 -2160) (1800 800))
+   R(l11 (-851 -401) (2 2))
+   R(l5 (-651 859) (425 950))
+  )
+  N(4
+   R(l3 (-100 4500) (2000 3500))
+  )
+  N(5 I(IN)
+   R(l4 (725 2860) (250 1940))
+   R(l4 (-525 -1850) (300 300))
+   R(l4 (-25 1550) (250 2000))
+   R(l4 (-250 -2000) (250 2000))
+   R(l4 (-250 -5390) (250 1450))
+   R(l8 (-465 150) (180 180))
+   R(l11 (-91 -91) (2 2))
+   R(l11 (-151 -151) (300 300))
+  )
+  N(6 I(SUBSTRATE))
+  P(1 I(VDD))
+  P(2 I(OUT))
+  P(3 I(VSS))
+  P(4)
+  P(5 I(IN))
+  P(6 I(SUBSTRATE))
+  D(1 D$PMOS$2
+   Y(850 5800)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0.6375)
+   E(AD 0.6375)
+   E(PS 3.85)
+   E(PD 3.85)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
+  )
+  D(2 D$NMOS$2
+   Y(850 2135)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0.40375)
+   E(AD 0.40375)
+   E(PS 2.75)
+   E(PD 2.75)
+   T(S 3)
+   T(G 5)
+   T(D 2)
+   T(B 6)
   )
  )
- circuit(RINGO RINGO match
-  xref(
-   net(1 6 match)
-   net(10 15 match)
-   net(2 7 match)
-   net(3 8 match)
-   net(4 9 match)
-   net(5 10 match)
-   net(6 11 match)
-   net(7 12 match)
-   net(8 13 match)
-   net(9 14 match)
-   net(14 4 match)
-   net(11 3 match)
-   net(13 5 match)
-   net(12 2 match)
-   net(15 1 match)
-   pin(3 3 match)
-   pin(0 2 match)
-   pin(2 4 match)
-   pin(1 1 match)
-   pin(4 0 match)
-   circuit(1 1 match)
-   circuit(10 10 match)
-   circuit(11 11 match)
-   circuit(12 12 match)
-   circuit(2 2 match)
-   circuit(3 3 match)
-   circuit(4 4 match)
-   circuit(5 5 match)
-   circuit(6 6 match)
-   circuit(7 7 match)
-   circuit(8 8 match)
-   circuit(9 9 match)
+ X(RINGO
+  R((0 350) (25800 7650))
+  N(1
+   R(l8 (4710 3010) (180 180))
+   R(l11 (-850 -240) (610 300))
+   R(l1 (-2550 1800) (425 1500))
+   R(l1 (950 -1500) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(2
+   R(l8 (6510 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(3
+   R(l8 (8310 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(4
+   R(l8 (10110 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(5
+   R(l8 (11910 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(6
+   R(l8 (13710 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(7
+   R(l8 (15510 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(8
+   R(l8 (17310 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(9
+   R(l8 (19110 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(10
+   R(l8 (20910 3010) (180 180))
+   R(l11 (-1140 -240) (900 300))
+   R(l1 (-1275 1800) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(11 I(FB)
+   R(l8 (22710 3010) (180 180))
+   R(l8 (-19700 720) (180 180))
+   R(l11 (18380 -1140) (900 300))
+   R(l11 (-19530 590) (320 320))
+   R(l11 (17820 -320) (320 320))
+   R(l12 (-18400 -260) (200 200))
+   R(l12 (17940 -200) (200 200))
+   R(l13 (-18040 -300) (17740 400))
+   R(l13 (-17921 -201) (2 2))
+   R(l13 (-221 -201) (400 400))
+   R(l13 (17740 -400) (400 400))
+   R(l1 (-245 850) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(12 I(VDD)
+   R(l3 (500 4500) (1400 3500))
+   R(l3 (-1900 -3500) (600 3500))
+   R(l3 (23300 -3500) (1400 3500))
+   R(l3 (-100 -3500) (600 3500))
+   R(l8 (-24690 -1240) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (23220 370) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l11 (-21741 859) (2 2))
+   R(l11 (-2351 -451) (1200 800))
+   R(l11 (-750 -1450) (300 1400))
+   R(l11 (-101 -351) (2 2))
+   R(l11 (-1251 -401) (600 800))
+   R(l11 (23400 -800) (1200 800))
+   R(l11 (-750 -1450) (300 1400))
+   R(l11 (-101 -351) (2 2))
+   R(l11 (549 -401) (600 800))
+   R(l1 (-23025 -2550) (425 1500))
+   R(l1 (-400 -1500) (425 1500))
+   R(l1 (1275 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l1 (1375 -1500) (425 1500))
+   R(l9 (-21975 -450) (500 1500))
+   R(l9 (22900 -1500) (500 1500))
+  )
+  N(13 I(OUT)
+   R(l11 (23440 3840) (320 320))
+   R(l12 (-260 -260) (200 200))
+   R(l13 (-101 -101) (2 2))
+   R(l13 (-201 -201) (400 400))
+   R(l1 (-625 850) (425 1500))
+   R(l5 (-425 -4890) (425 950))
+  )
+  N(14 I(ENABLE)
+   R(l8 (2510 3010) (180 180))
+   R(l11 (-250 -250) (320 320))
+   R(l12 (-260 -260) (200 200))
+   R(l13 (-101 -101) (2 2))
+   R(l13 (-201 -201) (400 400))
+  )
+  N(15 I(VSS)
+   R(l8 (1110 1610) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l8 (23220 370) (180 180))
+   R(l8 (-180 -1280) (180 180))
+   R(l8 (-180 370) (180 180))
+   R(l11 (-21741 -391) (2 2))
+   R(l11 (-1901 -401) (300 1400))
+   R(l11 (-750 -1450) (1200 800))
+   R(l11 (-551 -401) (2 2))
+   R(l11 (-1251 -401) (600 800))
+   R(l11 (23850 -750) (300 1400))
+   R(l11 (-750 -1450) (1200 800))
+   R(l11 (-551 -401) (2 2))
+   R(l11 (549 -401) (600 800))
+   R(l5 (-23700 460) (425 950))
+   R(l5 (1975 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l5 (1375 -950) (425 950))
+   R(l10 (-21975 -2210) (500 1500))
+   R(l10 (22900 -1500) (500 1500))
+  )
+  P(11 I(FB))
+  P(12 I(VDD))
+  P(13 I(OUT))
+  P(14 I(ENABLE))
+  P(15 I(VSS))
+  X(1 ND2X1 Y(1800 0)
+   P(0 12)
+   P(1 1)
+   P(2 15)
+   P(3 12)
+   P(4 11)
+   P(5 14)
+   P(6 15)
+  )
+  X(2 INVX1 Y(4200 0)
+   P(0 12)
+   P(1 2)
+   P(2 15)
+   P(3 12)
+   P(4 1)
+   P(5 15)
+  )
+  X(3 INVX1 Y(6000 0)
+   P(0 12)
+   P(1 3)
+   P(2 15)
+   P(3 12)
+   P(4 2)
+   P(5 15)
+  )
+  X(4 INVX1 Y(7800 0)
+   P(0 12)
+   P(1 4)
+   P(2 15)
+   P(3 12)
+   P(4 3)
+   P(5 15)
+  )
+  X(5 INVX1 Y(9600 0)
+   P(0 12)
+   P(1 5)
+   P(2 15)
+   P(3 12)
+   P(4 4)
+   P(5 15)
+  )
+  X(6 INVX1 Y(11400 0)
+   P(0 12)
+   P(1 6)
+   P(2 15)
+   P(3 12)
+   P(4 5)
+   P(5 15)
+  )
+  X(7 INVX1 Y(13200 0)
+   P(0 12)
+   P(1 7)
+   P(2 15)
+   P(3 12)
+   P(4 6)
+   P(5 15)
+  )
+  X(8 INVX1 Y(15000 0)
+   P(0 12)
+   P(1 8)
+   P(2 15)
+   P(3 12)
+   P(4 7)
+   P(5 15)
+  )
+  X(9 INVX1 Y(16800 0)
+   P(0 12)
+   P(1 9)
+   P(2 15)
+   P(3 12)
+   P(4 8)
+   P(5 15)
+  )
+  X(10 INVX1 Y(18600 0)
+   P(0 12)
+   P(1 10)
+   P(2 15)
+   P(3 12)
+   P(4 9)
+   P(5 15)
+  )
+  X(11 INVX1 Y(20400 0)
+   P(0 12)
+   P(1 11)
+   P(2 15)
+   P(3 12)
+   P(4 10)
+   P(5 15)
+  )
+  X(12 INVX1 Y(22200 0)
+   P(0 12)
+   P(1 13)
+   P(2 15)
+   P(3 12)
+   P(4 11)
+   P(5 15)
+  )
+ )
+)
+H(
+ X(ND2X1
+  N(1 I(VDD))
+  N(2 I(OUT))
+  N(3 I(VSS))
+  N(4 I(NWELL))
+  N(5 I(B))
+  N(6 I(A))
+  N(7 I(BULK))
+  N(8 I('1'))
+  P(1)
+  P(2)
+  P(3)
+  P(4)
+  P(5)
+  P(6)
+  P(7)
+  D(1 PMOS
+   I($1)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 2)
+   T(G 6)
+   T(D 1)
+   T(B 4)
+  )
+  D(2 PMOS
+   I($2)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
+  )
+  D(3 NMOS
+   I($3)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 3)
+   T(G 6)
+   T(D 8)
+   T(B 7)
+  )
+  D(4 NMOS
+   I($4)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 8)
+   T(G 5)
+   T(D 2)
+   T(B 7)
+  )
+ )
+ X(INVX1
+  N(1 I(VDD))
+  N(2 I(OUT))
+  N(3 I(VSS))
+  N(4 I(NWELL))
+  N(5 I(IN))
+  N(6 I(BULK))
+  P(1)
+  P(2)
+  P(3)
+  P(4)
+  P(5)
+  P(6)
+  D(1 PMOS
+   I($1)
+   E(L 0.25)
+   E(W 1.5)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 1)
+   T(G 5)
+   T(D 2)
+   T(B 4)
+  )
+  D(2 NMOS
+   I($2)
+   E(L 0.25)
+   E(W 0.95)
+   E(AS 0)
+   E(AD 0)
+   E(PS 0)
+   E(PD 0)
+   T(S 3)
+   T(G 5)
+   T(D 2)
+   T(B 6)
+  )
+ )
+ X(RINGO
+  N(1 I(VSS))
+  N(2 I(VDD))
+  N(3 I(FB))
+  N(4 I(ENABLE))
+  N(5 I(OUT))
+  N(6 I('1'))
+  N(7 I('2'))
+  N(8 I('3'))
+  N(9 I('4'))
+  N(10 I('5'))
+  N(11 I('6'))
+  N(12 I('7'))
+  N(13 I('8'))
+  N(14 I('9'))
+  N(15 I('10'))
+  P(1)
+  P(2)
+  P(3)
+  P(4)
+  P(5)
+  X(1 ND2X1 I($1)
+   P(0 2)
+   P(1 6)
+   P(2 1)
+   P(3 2)
+   P(4 3)
+   P(5 4)
+   P(6 1)
+  )
+  X(2 INVX1 I($2)
+   P(0 2)
+   P(1 7)
+   P(2 1)
+   P(3 2)
+   P(4 6)
+   P(5 1)
+  )
+  X(3 INVX1 I($3)
+   P(0 2)
+   P(1 8)
+   P(2 1)
+   P(3 2)
+   P(4 7)
+   P(5 1)
+  )
+  X(4 INVX1 I($4)
+   P(0 2)
+   P(1 9)
+   P(2 1)
+   P(3 2)
+   P(4 8)
+   P(5 1)
+  )
+  X(5 INVX1 I($5)
+   P(0 2)
+   P(1 10)
+   P(2 1)
+   P(3 2)
+   P(4 9)
+   P(5 1)
+  )
+  X(6 INVX1 I($6)
+   P(0 2)
+   P(1 11)
+   P(2 1)
+   P(3 2)
+   P(4 10)
+   P(5 1)
+  )
+  X(7 INVX1 I($7)
+   P(0 2)
+   P(1 12)
+   P(2 1)
+   P(3 2)
+   P(4 11)
+   P(5 1)
+  )
+  X(8 INVX1 I($8)
+   P(0 2)
+   P(1 13)
+   P(2 1)
+   P(3 2)
+   P(4 12)
+   P(5 1)
+  )
+  X(9 INVX1 I($9)
+   P(0 2)
+   P(1 14)
+   P(2 1)
+   P(3 2)
+   P(4 13)
+   P(5 1)
+  )
+  X(10 INVX1 I($10)
+   P(0 2)
+   P(1 15)
+   P(2 1)
+   P(3 2)
+   P(4 14)
+   P(5 1)
+  )
+  X(11 INVX1 I($11)
+   P(0 2)
+   P(1 3)
+   P(2 1)
+   P(3 2)
+   P(4 15)
+   P(5 1)
+  )
+  X(12 INVX1 I($12)
+   P(0 2)
+   P(1 5)
+   P(2 1)
+   P(3 2)
+   P(4 3)
+   P(5 1)
+  )
+ )
+)
+Z(
+ X(INVX1 INVX1 1
+  Z(
+   N(4 4 1)
+   N(5 5 1)
+   N(2 2 1)
+   N(6 6 1)
+   N(1 1 1)
+   N(3 3 1)
+   P(3 3 1)
+   P(4 4 1)
+   P(1 1 1)
+   P(5 5 1)
+   P(0 0 1)
+   P(2 2 1)
+   D(1 1 1)
+   D(2 2 1)
+  )
+ )
+ X(ND2X1 ND2X1 1
+  Z(
+   N(8 8 1)
+   N(4 4 1)
+   N(6 6 1)
+   N(5 5 1)
+   N(2 2 1)
+   N(7 7 1)
+   N(1 1 1)
+   N(3 3 1)
+   P(3 3 1)
+   P(5 5 1)
+   P(4 4 1)
+   P(1 1 1)
+   P(6 6 1)
+   P(0 0 1)
+   P(2 2 1)
+   D(1 1 1)
+   D(2 2 1)
+   D(3 3 1)
+   D(4 4 1)
+  )
+ )
+ X(RINGO RINGO 1
+  Z(
+   N(1 6 1)
+   N(10 15 1)
+   N(2 7 1)
+   N(3 8 1)
+   N(4 9 1)
+   N(5 10 1)
+   N(6 11 1)
+   N(7 12 1)
+   N(8 13 1)
+   N(9 14 1)
+   N(14 4 1)
+   N(11 3 1)
+   N(13 5 1)
+   N(12 2 1)
+   N(15 1 1)
+   P(3 3 1)
+   P(0 2 1)
+   P(2 4 1)
+   P(1 1 1)
+   P(4 0 1)
+   X(1 1 1)
+   X(10 10 1)
+   X(11 11 1)
+   X(12 12 1)
+   X(2 2 1)
+   X(3 3 1)
+   X(4 4 1)
+   X(5 5 1)
+   X(6 6 1)
+   X(7 7 1)
+   X(8 8 1)
+   X(9 9 1)
   )
  )
 )
diff --git a/testdata/lvs/ringo_simple_io2.l2n b/testdata/lvs/ringo_simple_io2.l2n
index 7dd408743..7bf5f3726 100644
--- a/testdata/lvs/ringo_simple_io2.l2n
+++ b/testdata/lvs/ringo_simple_io2.l2n
@@ -1,626 +1,580 @@
 #%l2n-klayout
-top(RINGO)
-unit(0.001)
-
-# Layer section
-# This section lists the mask layers (drawing or derived) and their connections.
-
-# Mask layers
-layer(l3 '1/0')
-layer(l4 '5/0')
-layer(l8 '8/0')
-layer(l11 '9/0')
-layer(l12 '10/0')
-layer(l13 '11/0')
-layer(l7)
-layer(l1)
-layer(l9)
-layer(l5)
-layer(l10)
-
-# Mask layer connectivity
-connect(l3 l3 l9)
-connect(l4 l4 l8)
-connect(l8 l4 l8 l11 l1 l9 l5 l10)
-connect(l11 l8 l11 l12)
-connect(l12 l11 l12 l13)
-connect(l13 l12 l13)
-connect(l7 l7)
-connect(l1 l8 l1)
-connect(l9 l3 l8 l9)
-connect(l5 l8 l5)
-connect(l10 l8 l10)
-
-# Global nets and connectivity
-global(l7 SUBSTRATE)
-global(l10 SUBSTRATE)
-
-# Device class section
-class(PMOS MOS4)
-class(NMOS MOS4)
-
-# Device abstracts section
-# Device abstracts list the pin shapes of the devices.
-device(D$PMOS PMOS
- terminal(S
-  rect(l1 (-550 -750) (425 1500))
+W(RINGO)
+U(0.001)
+L(l3 '1/0')
+L(l4 '5/0')
+L(l8 '8/0')
+L(l11 '9/0')
+L(l12 '10/0')
+L(l13 '11/0')
+L(l7)
+L(l1)
+L(l9)
+L(l5)
+L(l10)
+C(l3 l3 l9)
+C(l4 l4 l8)
+C(l8 l4 l8 l11 l1 l9 l5 l10)
+C(l11 l8 l11 l12)
+C(l12 l11 l12 l13)
+C(l13 l12 l13)
+C(l7 l7)
+C(l1 l8 l1)
+C(l9 l3 l8 l9)
+C(l5 l8 l5)
+C(l10 l8 l10)
+G(l7 SUBSTRATE)
+G(l10 SUBSTRATE)
+D(D$PMOS PMOS
+ T(S
+  R(l1 (-550 -750) (425 1500))
  )
- terminal(G
-  rect(l4 (-125 -750) (250 1500))
+ T(G
+  R(l4 (-125 -750) (250 1500))
  )
- terminal(D
-  rect(l1 (125 -750) (450 1500))
+ T(D
+  R(l1 (125 -750) (450 1500))
  )
- terminal(B
-  rect(l3 (-125 -750) (250 1500))
+ T(B
+  R(l3 (-125 -750) (250 1500))
  )
 )
-device(D$PMOS$1 PMOS
- terminal(S
-  rect(l1 (-575 -750) (450 1500))
+D(D$PMOS$1 PMOS
+ T(S
+  R(l1 (-575 -750) (450 1500))
  )
- terminal(G
-  rect(l4 (-125 -750) (250 1500))
+ T(G
+  R(l4 (-125 -750) (250 1500))
  )
- terminal(D
-  rect(l1 (125 -750) (425 1500))
+ T(D
+  R(l1 (125 -750) (425 1500))
  )
- terminal(B
-  rect(l3 (-125 -750) (250 1500))
+ T(B
+  R(l3 (-125 -750) (250 1500))
  )
 )
-device(D$PMOS$2 PMOS
- terminal(S
-  rect(l1 (-550 -750) (425 1500))
+D(D$PMOS$2 PMOS
+ T(S
+  R(l1 (-550 -750) (425 1500))
  )
- terminal(G
-  rect(l4 (-125 -750) (250 1500))
+ T(G
+  R(l4 (-125 -750) (250 1500))
  )
- terminal(D
-  rect(l1 (125 -750) (425 1500))
+ T(D
+  R(l1 (125 -750) (425 1500))
  )
- terminal(B
-  rect(l3 (-125 -750) (250 1500))
+ T(B
+  R(l3 (-125 -750) (250 1500))
  )
 )
-device(D$NMOS NMOS
- terminal(S
-  rect(l5 (-550 -475) (425 950))
+D(D$NMOS NMOS
+ T(S
+  R(l5 (-550 -475) (425 950))
  )
- terminal(G
-  rect(l4 (-125 -475) (250 950))
+ T(G
+  R(l4 (-125 -475) (250 950))
  )
- terminal(D
-  rect(l5 (125 -475) (450 950))
+ T(D
+  R(l5 (125 -475) (450 950))
  )
- terminal(B
-  rect(l7 (-125 -475) (250 950))
+ T(B
+  R(l7 (-125 -475) (250 950))
  )
 )
-device(D$NMOS$1 NMOS
- terminal(S
-  rect(l5 (-575 -475) (450 950))
+D(D$NMOS$1 NMOS
+ T(S
+  R(l5 (-575 -475) (450 950))
  )
- terminal(G
-  rect(l4 (-125 -475) (250 950))
+ T(G
+  R(l4 (-125 -475) (250 950))
  )
- terminal(D
-  rect(l5 (125 -475) (425 950))
+ T(D
+  R(l5 (125 -475) (425 950))
  )
- terminal(B
-  rect(l7 (-125 -475) (250 950))
+ T(B
+  R(l7 (-125 -475) (250 950))
  )
 )
-device(D$NMOS$2 NMOS
- terminal(S
-  rect(l5 (-550 -475) (425 950))
+D(D$NMOS$2 NMOS
+ T(S
+  R(l5 (-550 -475) (425 950))
  )
- terminal(G
-  rect(l4 (-125 -475) (250 950))
+ T(G
+  R(l4 (-125 -475) (250 950))
  )
- terminal(D
-  rect(l5 (125 -475) (425 950))
+ T(D
+  R(l5 (125 -475) (425 950))
  )
- terminal(B
-  rect(l7 (-125 -475) (250 950))
+ T(B
+  R(l7 (-125 -475) (250 950))
  )
 )
-
-# Circuit section
-# Circuits are the hierarchical building blocks of the netlist.
-circuit(ND2X1
-
- # Circuit boundary
- rect((-100 400) (2600 7600))
-
- # Nets with their geometries
- net(1 name(VDD)
-  rect(l8 (1110 5160) (180 180))
-  rect(l8 (-180 920) (180 180))
-  rect(l8 (-180 -730) (180 180))
-  rect(l11 (-240 -790) (300 1700))
-  rect(l11 (-1350 0) (2400 800))
-  rect(l11 (-1151 -401) (2 2))
-  rect(l1 (-276 -2151) (425 1500))
-  rect(l1 (-400 -1500) (425 1500))
+X(ND2X1
+ R((-100 400) (2600 7600))
+ N(1 I(VDD)
+  R(l8 (1110 5160) (180 180))
+  R(l8 (-180 920) (180 180))
+  R(l8 (-180 -730) (180 180))
+  R(l11 (-240 -790) (300 1700))
+  R(l11 (-1350 0) (2400 800))
+  R(l11 (-1151 -401) (2 2))
+  R(l1 (-276 -2151) (425 1500))
+  R(l1 (-400 -1500) (425 1500))
  )
- net(2 name(OUT)
-  rect(l8 (1810 1770) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l8 (-1580 3760) (180 180))
-  rect(l8 (-180 -730) (180 180))
-  rect(l8 (-180 -730) (180 180))
-  rect(l8 (1220 920) (180 180))
-  rect(l8 (-180 -1280) (180 180))
-  rect(l8 (-180 370) (180 180))
-  polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
-  rect(l11 (-110 1390) (300 1400))
-  polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
-  rect(l11 (-141 -501) (2 2))
-  rect(l11 (-1751 1099) (300 1400))
-  rect(l11 (1100 -1700) (300 300))
-  rect(l11 (-300 0) (300 1400))
-  rect(l1 (-1750 -1450) (425 1500))
-  rect(l1 (950 -1500) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(2 I(OUT)
+  R(l8 (1810 1770) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l8 (-1580 3760) (180 180))
+  R(l8 (-180 -730) (180 180))
+  R(l8 (-180 -730) (180 180))
+  R(l8 (1220 920) (180 180))
+  R(l8 (-180 -1280) (180 180))
+  R(l8 (-180 370) (180 180))
+  Q(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
+  R(l11 (-110 1390) (300 1400))
+  Q(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
+  R(l11 (-141 -501) (2 2))
+  R(l11 (-1751 1099) (300 1400))
+  R(l11 (1100 -1700) (300 300))
+  R(l11 (-300 0) (300 1400))
+  R(l1 (-1750 -1450) (425 1500))
+  R(l1 (950 -1500) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(3 name(VSS)
-  rect(l8 (410 1770) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l11 (-240 -1300) (300 1360))
-  rect(l11 (-650 -2160) (2400 800))
-  rect(l11 (-1151 -401) (2 2))
-  rect(l5 (-951 859) (425 950))
+ N(3 I(VSS)
+  R(l8 (410 1770) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l11 (-240 -1300) (300 1360))
+  R(l11 (-650 -2160) (2400 800))
+  R(l11 (-1151 -401) (2 2))
+  R(l5 (-951 859) (425 950))
  )
- net(4
-  rect(l3 (-100 4500) (2600 3500))
+ N(4
+  R(l3 (-100 4500) (2600 3500))
  )
- net(5 name(B)
-  rect(l4 (1425 2860) (250 1940))
-  rect(l4 (-345 -950) (300 300))
-  rect(l4 (-205 650) (250 2000))
-  rect(l4 (-250 -2000) (250 2000))
-  rect(l4 (-250 -5390) (250 1450))
-  rect(l8 (-285 1050) (180 180))
-  rect(l11 (-71 -91) (2 2))
-  rect(l11 (-171 -151) (300 300))
+ N(5 I(B)
+  R(l4 (1425 2860) (250 1940))
+  R(l4 (-345 -950) (300 300))
+  R(l4 (-205 650) (250 2000))
+  R(l4 (-250 -2000) (250 2000))
+  R(l4 (-250 -5390) (250 1450))
+  R(l8 (-285 1050) (180 180))
+  R(l11 (-71 -91) (2 2))
+  R(l11 (-171 -151) (300 300))
  )
- net(6 name(A)
-  rect(l4 (725 2860) (250 1940))
-  rect(l4 (-325 -1850) (300 300))
-  rect(l4 (-225 1550) (250 2000))
-  rect(l4 (-250 -2000) (250 2000))
-  rect(l4 (-250 -5390) (250 1450))
-  rect(l8 (-265 150) (180 180))
-  rect(l11 (-91 -91) (2 2))
-  rect(l11 (-151 -151) (300 300))
+ N(6 I(A)
+  R(l4 (725 2860) (250 1940))
+  R(l4 (-325 -1850) (300 300))
+  R(l4 (-225 1550) (250 2000))
+  R(l4 (-250 -2000) (250 2000))
+  R(l4 (-250 -5390) (250 1450))
+  R(l8 (-265 150) (180 180))
+  R(l11 (-91 -91) (2 2))
+  R(l11 (-151 -151) (300 300))
  )
- net(7 name(SUBSTRATE))
- net(8
-  rect(l5 (975 1660) (425 950))
-  rect(l5 (-400 -950) (425 950))
+ N(7 I(SUBSTRATE))
+ N(8
+  R(l5 (975 1660) (425 950))
+  R(l5 (-400 -950) (425 950))
  )
-
- # Outgoing pins and their connections to nets
- pin(1 name(VDD))
- pin(2 name(OUT))
- pin(3 name(VSS))
- pin(4)
- pin(5 name(B))
- pin(6 name(A))
- pin(7 name(SUBSTRATE))
-
- # Devices and their connections
- device(1 D$PMOS
-  location(850 5800)
-  param(L 0.25)
-  param(W 1.5)
-  param(AS 0.6375)
-  param(AD 0.3375)
-  param(PS 3.85)
-  param(PD 1.95)
-  terminal(S 2)
-  terminal(G 6)
-  terminal(D 1)
-  terminal(B 4)
+ P(1 I(VDD))
+ P(2 I(OUT))
+ P(3 I(VSS))
+ P(4)
+ P(5 I(B))
+ P(6 I(A))
+ P(7 I(SUBSTRATE))
+ D(1 D$PMOS
+  Y(850 5800)
+  E(L 0.25)
+  E(W 1.5)
+  E(AS 0.6375)
+  E(AD 0.3375)
+  E(PS 3.85)
+  E(PD 1.95)
+  T(S 2)
+  T(G 6)
+  T(D 1)
+  T(B 4)
  )
- device(2 D$PMOS$1
-  location(1550 5800)
-  param(L 0.25)
-  param(W 1.5)
-  param(AS 0.3375)
-  param(AD 0.6375)
-  param(PS 1.95)
-  param(PD 3.85)
-  terminal(S 1)
-  terminal(G 5)
-  terminal(D 2)
-  terminal(B 4)
+ D(2 D$PMOS$1
+  Y(1550 5800)
+  E(L 0.25)
+  E(W 1.5)
+  E(AS 0.3375)
+  E(AD 0.6375)
+  E(PS 1.95)
+  E(PD 3.85)
+  T(S 1)
+  T(G 5)
+  T(D 2)
+  T(B 4)
  )
- device(3 D$NMOS
-  location(850 2135)
-  param(L 0.25)
-  param(W 0.95)
-  param(AS 0.40375)
-  param(AD 0.21375)
-  param(PS 2.75)
-  param(PD 1.4)
-  terminal(S 3)
-  terminal(G 6)
-  terminal(D 8)
-  terminal(B 7)
+ D(3 D$NMOS
+  Y(850 2135)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.40375)
+  E(AD 0.21375)
+  E(PS 2.75)
+  E(PD 1.4)
+  T(S 3)
+  T(G 6)
+  T(D 8)
+  T(B 7)
  )
- device(4 D$NMOS$1
-  location(1550 2135)
-  param(L 0.25)
-  param(W 0.95)
-  param(AS 0.21375)
-  param(AD 0.40375)
-  param(PS 1.4)
-  param(PD 2.75)
-  terminal(S 8)
-  terminal(G 5)
-  terminal(D 2)
-  terminal(B 7)
+ D(4 D$NMOS$1
+  Y(1550 2135)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.21375)
+  E(AD 0.40375)
+  E(PS 1.4)
+  E(PD 2.75)
+  T(S 8)
+  T(G 5)
+  T(D 2)
+  T(B 7)
  )
-
 )
-circuit(INVX1
-
- # Circuit boundary
- rect((-100 400) (2000 7600))
-
- # Nets with their geometries
- net(1 name(VDD)
-  rect(l8 (410 6260) (180 180))
-  rect(l8 (-180 -730) (180 180))
-  rect(l8 (-180 -730) (180 180))
-  rect(l11 (-240 -240) (300 1400))
-  rect(l11 (-650 300) (1800 800))
-  rect(l11 (-1450 -1100) (300 300))
-  rect(l11 (299 399) (2 2))
-  rect(l1 (-651 -2151) (425 1500))
+X(INVX1
+ R((-100 400) (2000 7600))
+ N(1 I(VDD)
+  R(l8 (410 6260) (180 180))
+  R(l8 (-180 -730) (180 180))
+  R(l8 (-180 -730) (180 180))
+  R(l11 (-240 -240) (300 1400))
+  R(l11 (-650 300) (1800 800))
+  R(l11 (-1450 -1100) (300 300))
+  R(l11 (299 399) (2 2))
+  R(l1 (-651 -2151) (425 1500))
  )
- net(2 name(OUT)
-  rect(l8 (1110 5160) (180 180))
-  rect(l8 (-180 920) (180 180))
-  rect(l8 (-180 -730) (180 180))
-  rect(l8 (-180 -4120) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l11 (-240 -790) (300 4790))
-  rect(l11 (-151 -2501) (2 2))
-  rect(l1 (-226 1049) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(2 I(OUT)
+  R(l8 (1110 5160) (180 180))
+  R(l8 (-180 920) (180 180))
+  R(l8 (-180 -730) (180 180))
+  R(l8 (-180 -4120) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l11 (-240 -790) (300 4790))
+  R(l11 (-151 -2501) (2 2))
+  R(l1 (-226 1049) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(3 name(VSS)
-  rect(l8 (410 1770) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l11 (-240 -1300) (300 1360))
-  rect(l11 (-650 -2160) (1800 800))
-  rect(l11 (-851 -401) (2 2))
-  rect(l5 (-651 859) (425 950))
+ N(3 I(VSS)
+  R(l8 (410 1770) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l11 (-240 -1300) (300 1360))
+  R(l11 (-650 -2160) (1800 800))
+  R(l11 (-851 -401) (2 2))
+  R(l5 (-651 859) (425 950))
  )
- net(4
-  rect(l3 (-100 4500) (2000 3500))
+ N(4
+  R(l3 (-100 4500) (2000 3500))
  )
- net(5 name(IN)
-  rect(l4 (725 2860) (250 1940))
-  rect(l4 (-525 -1850) (300 300))
-  rect(l4 (-25 1550) (250 2000))
-  rect(l4 (-250 -2000) (250 2000))
-  rect(l4 (-250 -5390) (250 1450))
-  rect(l8 (-465 150) (180 180))
-  rect(l11 (-91 -91) (2 2))
-  rect(l11 (-151 -151) (300 300))
+ N(5 I(IN)
+  R(l4 (725 2860) (250 1940))
+  R(l4 (-525 -1850) (300 300))
+  R(l4 (-25 1550) (250 2000))
+  R(l4 (-250 -2000) (250 2000))
+  R(l4 (-250 -5390) (250 1450))
+  R(l8 (-465 150) (180 180))
+  R(l11 (-91 -91) (2 2))
+  R(l11 (-151 -151) (300 300))
  )
- net(6 name(SUBSTRATE))
-
- # Outgoing pins and their connections to nets
- pin(1 name(VDD))
- pin(2 name(OUT))
- pin(3 name(VSS))
- pin(4)
- pin(5 name(IN))
- pin(6 name(SUBSTRATE))
-
- # Devices and their connections
- device(1 D$PMOS$2
-  location(850 5800)
-  param(L 0.25)
-  param(W 1.5)
-  param(AS 0.6375)
-  param(AD 0.6375)
-  param(PS 3.85)
-  param(PD 3.85)
-  terminal(S 1)
-  terminal(G 5)
-  terminal(D 2)
-  terminal(B 4)
+ N(6 I(SUBSTRATE))
+ P(1 I(VDD))
+ P(2 I(OUT))
+ P(3 I(VSS))
+ P(4)
+ P(5 I(IN))
+ P(6 I(SUBSTRATE))
+ D(1 D$PMOS$2
+  Y(850 5800)
+  E(L 0.25)
+  E(W 1.5)
+  E(AS 0.6375)
+  E(AD 0.6375)
+  E(PS 3.85)
+  E(PD 3.85)
+  T(S 1)
+  T(G 5)
+  T(D 2)
+  T(B 4)
  )
- device(2 D$NMOS$2
-  location(850 2135)
-  param(L 0.25)
-  param(W 0.95)
-  param(AS 0.40375)
-  param(AD 0.40375)
-  param(PS 2.75)
-  param(PD 2.75)
-  terminal(S 3)
-  terminal(G 5)
-  terminal(D 2)
-  terminal(B 6)
+ D(2 D$NMOS$2
+  Y(850 2135)
+  E(L 0.25)
+  E(W 0.95)
+  E(AS 0.40375)
+  E(AD 0.40375)
+  E(PS 2.75)
+  E(PD 2.75)
+  T(S 3)
+  T(G 5)
+  T(D 2)
+  T(B 6)
  )
-
 )
-circuit(RINGO
-
- # Circuit boundary
- rect((0 350) (25800 7650))
-
- # Nets with their geometries
- net(1
-  rect(l8 (4710 3010) (180 180))
-  rect(l11 (-850 -240) (610 300))
-  rect(l1 (-2550 1800) (425 1500))
-  rect(l1 (950 -1500) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+X(RINGO
+ R((0 350) (25800 7650))
+ N(1
+  R(l8 (4710 3010) (180 180))
+  R(l11 (-850 -240) (610 300))
+  R(l1 (-2550 1800) (425 1500))
+  R(l1 (950 -1500) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(2
-  rect(l8 (6510 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(2
+  R(l8 (6510 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(3
-  rect(l8 (8310 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(3
+  R(l8 (8310 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(4
-  rect(l8 (10110 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(4
+  R(l8 (10110 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(5
-  rect(l8 (11910 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(5
+  R(l8 (11910 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(6
-  rect(l8 (13710 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(6
+  R(l8 (13710 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(7
-  rect(l8 (15510 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(7
+  R(l8 (15510 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(8
-  rect(l8 (17310 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(8
+  R(l8 (17310 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(9
-  rect(l8 (19110 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(9
+  R(l8 (19110 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(10
-  rect(l8 (20910 3010) (180 180))
-  rect(l11 (-1140 -240) (900 300))
-  rect(l1 (-1275 1800) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(10
+  R(l8 (20910 3010) (180 180))
+  R(l11 (-1140 -240) (900 300))
+  R(l1 (-1275 1800) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(11 name(FB)
-  rect(l8 (22710 3010) (180 180))
-  rect(l8 (-19700 720) (180 180))
-  rect(l11 (18380 -1140) (900 300))
-  rect(l11 (-19530 590) (320 320))
-  rect(l11 (17820 -320) (320 320))
-  rect(l12 (-18400 -260) (200 200))
-  rect(l12 (17940 -200) (200 200))
-  rect(l13 (-18040 -300) (17740 400))
-  rect(l13 (-17921 -201) (2 2))
-  rect(l13 (-221 -201) (400 400))
-  rect(l13 (17740 -400) (400 400))
-  rect(l1 (-245 850) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(11 I(FB)
+  R(l8 (22710 3010) (180 180))
+  R(l8 (-19700 720) (180 180))
+  R(l11 (18380 -1140) (900 300))
+  R(l11 (-19530 590) (320 320))
+  R(l11 (17820 -320) (320 320))
+  R(l12 (-18400 -260) (200 200))
+  R(l12 (17940 -200) (200 200))
+  R(l13 (-18040 -300) (17740 400))
+  R(l13 (-17921 -201) (2 2))
+  R(l13 (-221 -201) (400 400))
+  R(l13 (17740 -400) (400 400))
+  R(l1 (-245 850) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(12 name(VDD)
-  rect(l3 (500 4500) (1400 3500))
-  rect(l3 (-1900 -3500) (600 3500))
-  rect(l3 (23300 -3500) (1400 3500))
-  rect(l3 (-100 -3500) (600 3500))
-  rect(l8 (-24690 -1240) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l8 (-180 -1280) (180 180))
-  rect(l8 (23220 370) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l8 (-180 -1280) (180 180))
-  rect(l11 (-21741 859) (2 2))
-  rect(l11 (-2351 -451) (1200 800))
-  rect(l11 (-750 -1450) (300 1400))
-  rect(l11 (-101 -351) (2 2))
-  rect(l11 (-1251 -401) (600 800))
-  rect(l11 (23400 -800) (1200 800))
-  rect(l11 (-750 -1450) (300 1400))
-  rect(l11 (-101 -351) (2 2))
-  rect(l11 (549 -401) (600 800))
-  rect(l1 (-23025 -2550) (425 1500))
-  rect(l1 (-400 -1500) (425 1500))
-  rect(l1 (1275 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l1 (1375 -1500) (425 1500))
-  rect(l9 (-21975 -450) (500 1500))
-  rect(l9 (22900 -1500) (500 1500))
+ N(12 I(VDD)
+  R(l3 (500 4500) (1400 3500))
+  R(l3 (-1900 -3500) (600 3500))
+  R(l3 (23300 -3500) (1400 3500))
+  R(l3 (-100 -3500) (600 3500))
+  R(l8 (-24690 -1240) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l8 (-180 -1280) (180 180))
+  R(l8 (23220 370) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l8 (-180 -1280) (180 180))
+  R(l11 (-21741 859) (2 2))
+  R(l11 (-2351 -451) (1200 800))
+  R(l11 (-750 -1450) (300 1400))
+  R(l11 (-101 -351) (2 2))
+  R(l11 (-1251 -401) (600 800))
+  R(l11 (23400 -800) (1200 800))
+  R(l11 (-750 -1450) (300 1400))
+  R(l11 (-101 -351) (2 2))
+  R(l11 (549 -401) (600 800))
+  R(l1 (-23025 -2550) (425 1500))
+  R(l1 (-400 -1500) (425 1500))
+  R(l1 (1275 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l1 (1375 -1500) (425 1500))
+  R(l9 (-21975 -450) (500 1500))
+  R(l9 (22900 -1500) (500 1500))
  )
- net(13 name(OUT)
-  rect(l11 (23440 3840) (320 320))
-  rect(l12 (-260 -260) (200 200))
-  rect(l13 (-101 -101) (2 2))
-  rect(l13 (-201 -201) (400 400))
-  rect(l1 (-625 850) (425 1500))
-  rect(l5 (-425 -4890) (425 950))
+ N(13 I(OUT)
+  R(l11 (23440 3840) (320 320))
+  R(l12 (-260 -260) (200 200))
+  R(l13 (-101 -101) (2 2))
+  R(l13 (-201 -201) (400 400))
+  R(l1 (-625 850) (425 1500))
+  R(l5 (-425 -4890) (425 950))
  )
- net(14 name(ENABLE)
-  rect(l8 (2510 3010) (180 180))
-  rect(l11 (-250 -250) (320 320))
-  rect(l12 (-260 -260) (200 200))
-  rect(l13 (-101 -101) (2 2))
-  rect(l13 (-201 -201) (400 400))
+ N(14 I(ENABLE)
+  R(l8 (2510 3010) (180 180))
+  R(l11 (-250 -250) (320 320))
+  R(l12 (-260 -260) (200 200))
+  R(l13 (-101 -101) (2 2))
+  R(l13 (-201 -201) (400 400))
  )
- net(15 name(VSS)
-  rect(l8 (1110 1610) (180 180))
-  rect(l8 (-180 -1280) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l8 (23220 370) (180 180))
-  rect(l8 (-180 -1280) (180 180))
-  rect(l8 (-180 370) (180 180))
-  rect(l11 (-21741 -391) (2 2))
-  rect(l11 (-1901 -401) (300 1400))
-  rect(l11 (-750 -1450) (1200 800))
-  rect(l11 (-551 -401) (2 2))
-  rect(l11 (-1251 -401) (600 800))
-  rect(l11 (23850 -750) (300 1400))
-  rect(l11 (-750 -1450) (1200 800))
-  rect(l11 (-551 -401) (2 2))
-  rect(l11 (549 -401) (600 800))
-  rect(l5 (-23700 460) (425 950))
-  rect(l5 (1975 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l5 (1375 -950) (425 950))
-  rect(l10 (-21975 -2210) (500 1500))
-  rect(l10 (22900 -1500) (500 1500))
+ N(15 I(VSS)
+  R(l8 (1110 1610) (180 180))
+  R(l8 (-180 -1280) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l8 (23220 370) (180 180))
+  R(l8 (-180 -1280) (180 180))
+  R(l8 (-180 370) (180 180))
+  R(l11 (-21741 -391) (2 2))
+  R(l11 (-1901 -401) (300 1400))
+  R(l11 (-750 -1450) (1200 800))
+  R(l11 (-551 -401) (2 2))
+  R(l11 (-1251 -401) (600 800))
+  R(l11 (23850 -750) (300 1400))
+  R(l11 (-750 -1450) (1200 800))
+  R(l11 (-551 -401) (2 2))
+  R(l11 (549 -401) (600 800))
+  R(l5 (-23700 460) (425 950))
+  R(l5 (1975 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l5 (1375 -950) (425 950))
+  R(l10 (-21975 -2210) (500 1500))
+  R(l10 (22900 -1500) (500 1500))
  )
-
- # Outgoing pins and their connections to nets
- pin(11 name(FB))
- pin(12 name(VDD))
- pin(13 name(OUT))
- pin(14 name(ENABLE))
- pin(15 name(VSS))
-
- # Subcircuits and their connections
- circuit(1 ND2X1 location(1800 0)
-  pin(0 12)
-  pin(1 1)
-  pin(2 15)
-  pin(3 12)
-  pin(4 11)
-  pin(5 14)
-  pin(6 15)
+ P(11 I(FB))
+ P(12 I(VDD))
+ P(13 I(OUT))
+ P(14 I(ENABLE))
+ P(15 I(VSS))
+ X(1 ND2X1 Y(1800 0)
+  P(0 12)
+  P(1 1)
+  P(2 15)
+  P(3 12)
+  P(4 11)
+  P(5 14)
+  P(6 15)
  )
- circuit(2 INVX1 location(4200 0)
-  pin(0 12)
-  pin(1 2)
-  pin(2 15)
-  pin(3 12)
-  pin(4 1)
-  pin(5 15)
+ X(2 INVX1 Y(4200 0)
+  P(0 12)
+  P(1 2)
+  P(2 15)
+  P(3 12)
+  P(4 1)
+  P(5 15)
  )
- circuit(3 INVX1 location(6000 0)
-  pin(0 12)
-  pin(1 3)
-  pin(2 15)
-  pin(3 12)
-  pin(4 2)
-  pin(5 15)
+ X(3 INVX1 Y(6000 0)
+  P(0 12)
+  P(1 3)
+  P(2 15)
+  P(3 12)
+  P(4 2)
+  P(5 15)
  )
- circuit(4 INVX1 location(7800 0)
-  pin(0 12)
-  pin(1 4)
-  pin(2 15)
-  pin(3 12)
-  pin(4 3)
-  pin(5 15)
+ X(4 INVX1 Y(7800 0)
+  P(0 12)
+  P(1 4)
+  P(2 15)
+  P(3 12)
+  P(4 3)
+  P(5 15)
  )
- circuit(5 INVX1 location(9600 0)
-  pin(0 12)
-  pin(1 5)
-  pin(2 15)
-  pin(3 12)
-  pin(4 4)
-  pin(5 15)
+ X(5 INVX1 Y(9600 0)
+  P(0 12)
+  P(1 5)
+  P(2 15)
+  P(3 12)
+  P(4 4)
+  P(5 15)
  )
- circuit(6 INVX1 location(11400 0)
-  pin(0 12)
-  pin(1 6)
-  pin(2 15)
-  pin(3 12)
-  pin(4 5)
-  pin(5 15)
+ X(6 INVX1 Y(11400 0)
+  P(0 12)
+  P(1 6)
+  P(2 15)
+  P(3 12)
+  P(4 5)
+  P(5 15)
  )
- circuit(7 INVX1 location(13200 0)
-  pin(0 12)
-  pin(1 7)
-  pin(2 15)
-  pin(3 12)
-  pin(4 6)
-  pin(5 15)
+ X(7 INVX1 Y(13200 0)
+  P(0 12)
+  P(1 7)
+  P(2 15)
+  P(3 12)
+  P(4 6)
+  P(5 15)
  )
- circuit(8 INVX1 location(15000 0)
-  pin(0 12)
-  pin(1 8)
-  pin(2 15)
-  pin(3 12)
-  pin(4 7)
-  pin(5 15)
+ X(8 INVX1 Y(15000 0)
+  P(0 12)
+  P(1 8)
+  P(2 15)
+  P(3 12)
+  P(4 7)
+  P(5 15)
  )
- circuit(9 INVX1 location(16800 0)
-  pin(0 12)
-  pin(1 9)
-  pin(2 15)
-  pin(3 12)
-  pin(4 8)
-  pin(5 15)
+ X(9 INVX1 Y(16800 0)
+  P(0 12)
+  P(1 9)
+  P(2 15)
+  P(3 12)
+  P(4 8)
+  P(5 15)
  )
- circuit(10 INVX1 location(18600 0)
-  pin(0 12)
-  pin(1 10)
-  pin(2 15)
-  pin(3 12)
-  pin(4 9)
-  pin(5 15)
+ X(10 INVX1 Y(18600 0)
+  P(0 12)
+  P(1 10)
+  P(2 15)
+  P(3 12)
+  P(4 9)
+  P(5 15)
  )
- circuit(11 INVX1 location(20400 0)
-  pin(0 12)
-  pin(1 11)
-  pin(2 15)
-  pin(3 12)
-  pin(4 10)
-  pin(5 15)
+ X(11 INVX1 Y(20400 0)
+  P(0 12)
+  P(1 11)
+  P(2 15)
+  P(3 12)
+  P(4 10)
+  P(5 15)
  )
- circuit(12 INVX1 location(22200 0)
-  pin(0 12)
-  pin(1 13)
-  pin(2 15)
-  pin(3 12)
-  pin(4 11)
-  pin(5 15)
+ X(12 INVX1 Y(22200 0)
+  P(0 12)
+  P(1 13)
+  P(2 15)
+  P(3 12)
+  P(4 11)
+  P(5 15)
  )
-
 )
diff --git a/testdata/lvs/ringo_simple_io2.lvs b/testdata/lvs/ringo_simple_io2.lvs
index 72200b9fd..bea93496f 100644
--- a/testdata/lvs/ringo_simple_io2.lvs
+++ b/testdata/lvs/ringo_simple_io2.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "RINGO")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 report_netlist($lvs_test_target_l2n)
 
 # Write extracted netlist to extracted.cir using a special
diff --git a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvs b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvs
index 954ff09f1..955544f56 100644
--- a/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvs
+++ b/testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "top")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 
 target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
 
diff --git a/testdata/lvs/ringo_simple_pin_swapping.lvs b/testdata/lvs/ringo_simple_pin_swapping.lvs
index 5d3c77627..d5cf46936 100644
--- a/testdata/lvs/ringo_simple_pin_swapping.lvs
+++ b/testdata/lvs/ringo_simple_pin_swapping.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "RINGO")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 
 target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
 
diff --git a/testdata/lvs/ringo_simple_same_device_classes.lvs b/testdata/lvs/ringo_simple_same_device_classes.lvs
index b516aaea5..da0ec1196 100644
--- a/testdata/lvs/ringo_simple_same_device_classes.lvs
+++ b/testdata/lvs/ringo_simple_same_device_classes.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "RINGO")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 
 writer = write_spice(true, false)
 target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
diff --git a/testdata/lvs/ringo_simple_simplification.lvs b/testdata/lvs/ringo_simple_simplification.lvs
index ff57709e5..9579e11cd 100644
--- a/testdata/lvs/ringo_simple_simplification.lvs
+++ b/testdata/lvs/ringo_simple_simplification.lvs
@@ -1,7 +1,7 @@
 
 source($lvs_test_source, "RINGO")
 
-report_lvs($lvs_test_target_lvsdb)
+report_lvs($lvs_test_target_lvsdb, true)
 
 target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
 
diff --git a/testdata/lvs/vexriscv.lvs b/testdata/lvs/vexriscv.lvs
index 79d4768fe..f9c4621bf 100644
--- a/testdata/lvs/vexriscv.lvs
+++ b/testdata/lvs/vexriscv.lvs
@@ -2,7 +2,7 @@
 source($lvs_test_source)
 
 # will get pretty big:
-# report_lvs($lvs_test_target_lvsdb)
+# report_lvs($lvs_test_target_lvsdb, true)
 
 target_netlist($lvs_test_target_cir, write_spice(true), "Extracted by KLayout")