New testdata, bugfix: considering the case of partial net formation through soft, upward inter-instance connections. Enhanced reporting (report multiple partial nets of the same circuit at different instances)

2026-08-29 01:14:35 +02:00 · 2024-03-21 21:31:20 +01:00
parent 366249645a
commit 917439b84e
5 changed files with 118 additions and 8 deletions
@@ -0,0 +1,13 @@
+* Extracted by KLayout
+
+.SUBCKT TOP A Q SUBSTRATE
+X$1 \$5 \$1 Q SUBSTRATE INV
+X$2 \$5 A \$1 SUBSTRATE INV
+.ENDS TOP
+
+.SUBCKT INV \$2 \$4 \$5 SUBSTRATE
+M$1 \$2 \$4 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
+M$2 SUBSTRATE \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
+ PS=3.45U PD=3.45U
+.ENDS INV
@@ -0,0 +1,93 @@
+
+$lvs_test_source && source($lvs_test_source)
+
+if $lvs_test_target_l2n
+  report_netlist($lvs_test_target_l2n)
+else
+  report_netlist
+end
+
+writer = write_spice(true, false)
+$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
+
+deep
+
+# Drawing layers
+
+nwell       = input(1, 0)
+active      = input(2, 0)
+nplus       = input(2, 1)
+pplus       = input(2, 2)
+poly        = input(3, 0)
+poly_lbl    = input(3, 1)
+diff_cont   = input(4, 0)
+poly_cont   = input(5, 0)
+metal1      = input(6, 0)
+metal1_lbl  = input(6, 1)
+via1        = input(7, 0)
+metal2      = input(8, 0)
+metal2_lbl  = input(8, 1)
+
+# Bulk layer for terminal provisioning
+
+bulk        = polygon_layer
+
+psd = nil
+nsd = nil
+
+# Computed layers
+
+active_in_nwell       = active & nwell
+pactive               = active_in_nwell & pplus
+ntie                  = active_in_nwell & nplus
+pgate                 = pactive & poly
+psd                   = pactive - pgate
+
+active_outside_nwell  = active - nwell
+nactive               = active_outside_nwell & nplus
+ptie                  = active_outside_nwell & pplus
+ngate                 = nactive & poly
+nsd                   = nactive - ngate
+
+# Device extraction
+
+# PMOS transistor device extraction
+extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
+                                "tS" => psd, "tD" => psd, "tG" => poly })
+
+# NMOS transistor device extraction
+extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
+                                "tS" => nsd, "tD" => nsd, "tG" => poly })
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+
+soft_connect(diff_cont, psd)
+soft_connect(diff_cont, nsd)
+soft_connect(diff_cont, ptie)
+soft_connect(diff_cont, ntie)
+soft_connect(ntie, nwell)
+soft_connect(poly_cont, poly)
+
+connect(diff_cont, metal1)
+connect(poly_cont, metal1)
+connect(metal1, via1)
+connect(via1, metal2)
+
+# attach labels
+connect(poly, poly_lbl)
+connect(metal1, metal1_lbl)
+connect(metal2, metal2_lbl)
+
+# Global
+connect_global(bulk, "SUBSTRATE")
+soft_connect_global(ptie, "SUBSTRATE")
+
+# Netlist section (NOTE: we only check log here)
+# for debugging: _make_soft_connection_diodes(true)
+netlist
+
+netlist.simplify
+
+