New testdata, bugfix: considering the case of partial net formation through soft, upward inter-instance connections. Enhanced reporting (report multiple partial nets of the same circuit at different instances)

This commit is contained in:
Matthias Koefferlein 2024-03-21 21:31:20 +01:00
parent 366249645a
commit 917439b84e
5 changed files with 118 additions and 8 deletions

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@ -41,9 +41,7 @@ SoftConnectionNetGraph::SoftConnectionNetGraph ()
void SoftConnectionNetGraph::add (const db::Net *net, SoftConnectionPinDir dir, const db::Pin *pin, size_t partial_net_count)
{
// limiting the partial net count to 1 means we report errors only once in the
// hierarchy, not on every level
m_partial_net_count += std::min (size_t (1), partial_net_count);
m_partial_net_count += partial_net_count;
// this is where we make the decision about the partial nets ...
if (! pin && dir == SoftConnectionPinDir::down ()) {
@ -188,13 +186,13 @@ SoftConnectionInfo::representative_polygon (const db::Net *net, const db::Layout
return db::DPolygon (bbox);
}
void SoftConnectionInfo::report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &net_graph, db::LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<const db::Net *> &seen)
void SoftConnectionInfo::report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &net_graph, db::LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<std::pair<const db::Net *, db::DCplxTrans> > &seen)
{
for (auto cc = net_graph.begin_clusters (); cc != net_graph.end_clusters (); ++cc) {
const db::Net *net = circuit->net_by_cluster_id (cc->first);
if (! seen.insert (net).second) {
if (! seen.insert (std::make_pair (net, trans)).second) {
continue;
}
@ -263,7 +261,7 @@ void SoftConnectionInfo::report (db::LayoutToNetlist &l2n)
l2n.log_entry (log_entry);
int index = 0;
std::set<const db::Net *> seen;
std::set<std::pair<const db::Net *, db::DCplxTrans> > seen;
report_partial_nets (c.operator-> (), *sc, l2n, c->name (), db::DCplxTrans (), c->name (), index, seen);
}
@ -390,7 +388,13 @@ void SoftConnectionInfo::get_net_connections_through_subcircuit (const db::SubCi
const SoftConnectionNetGraph *scci = sci.get_net_graph_per_pin (pin);
if (scci) {
partial_net_count += scci->partial_net_count ();
// NOTE: limiting the partial net count here means we do report a partially connected once in the
// hierarchy, not on every level.
// Say, if you have two subcircuits, one (A) having 2 partial nets and the other (B) none. Then
// (A) would be reported to partial nets only and when combining (A) and (B) we just need to check
// whether B would also have partial nets. By not taking 2 + 0, but 1 + 0 the combination of (A)
// and (B) does not give an error (error = number of partial nets > 1).
partial_net_count += std::min (size_t (1), scci->partial_net_count ());
for (auto p = scci->begin_pins (); p != scci->end_pins (); ++p) {
if (*p != pin->id ()) {

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@ -344,7 +344,7 @@ private:
*/
std::set<size_t> net_connections_through_subcircuits (const db::Net *net, size_t &partial_net_count);
void report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &cluster_info, LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<const Net *> &seen);
void report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &cluster_info, LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<std::pair<const db::Net *, db::DCplxTrans> > &seen);
db::DPolygon representative_polygon (const db::Net *net, const db::LayoutToNetlist &l2n, const db::CplxTrans &trans);
};

13
testdata/lvs/soft_connect4.cir vendored Normal file
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@ -0,0 +1,13 @@
* Extracted by KLayout
.SUBCKT TOP A Q SUBSTRATE
X$1 \$5 \$1 Q SUBSTRATE INV
X$2 \$5 A \$1 SUBSTRATE INV
.ENDS TOP
.SUBCKT INV \$2 \$4 \$5 SUBSTRATE
M$1 \$2 \$4 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 SUBSTRATE \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
+ PS=3.45U PD=3.45U
.ENDS INV

BIN
testdata/lvs/soft_connect4.gds vendored Normal file

Binary file not shown.

93
testdata/lvs/soft_connect4.lvs vendored Normal file
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@ -0,0 +1,93 @@
$lvs_test_source && source($lvs_test_source)
if $lvs_test_target_l2n
report_netlist($lvs_test_target_l2n)
else
report_netlist
end
writer = write_spice(true, false)
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
nplus = input(2, 1)
pplus = input(2, 2)
poly = input(3, 0)
poly_lbl = input(3, 1)
diff_cont = input(4, 0)
poly_cont = input(5, 0)
metal1 = input(6, 0)
metal1_lbl = input(6, 1)
via1 = input(7, 0)
metal2 = input(8, 0)
metal2_lbl = input(8, 1)
# Bulk layer for terminal provisioning
bulk = polygon_layer
psd = nil
nsd = nil
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell & pplus
ntie = active_in_nwell & nplus
pgate = pactive & poly
psd = pactive - pgate
active_outside_nwell = active - nwell
nactive = active_outside_nwell & nplus
ptie = active_outside_nwell & pplus
ngate = nactive & poly
nsd = nactive - ngate
# Device extraction
# PMOS transistor device extraction
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
"tS" => psd, "tD" => psd, "tG" => poly })
# NMOS transistor device extraction
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
"tS" => nsd, "tD" => nsd, "tG" => poly })
# Define connectivity for netlist extraction
# Inter-layer
soft_connect(diff_cont, psd)
soft_connect(diff_cont, nsd)
soft_connect(diff_cont, ptie)
soft_connect(diff_cont, ntie)
soft_connect(ntie, nwell)
soft_connect(poly_cont, poly)
connect(diff_cont, metal1)
connect(poly_cont, metal1)
connect(metal1, via1)
connect(via1, metal2)
# attach labels
connect(poly, poly_lbl)
connect(metal1, metal1_lbl)
connect(metal2, metal2_lbl)
# Global
connect_global(bulk, "SUBSTRATE")
soft_connect_global(ptie, "SUBSTRATE")
# Netlist section (NOTE: we only check log here)
# for debugging: _make_soft_connection_diodes(true)
netlist
netlist.simplify