mirror of https://github.com/KLayout/klayout.git
New testdata, bugfix: considering the case of partial net formation through soft, upward inter-instance connections. Enhanced reporting (report multiple partial nets of the same circuit at different instances)
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366249645a
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@ -41,9 +41,7 @@ SoftConnectionNetGraph::SoftConnectionNetGraph ()
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void SoftConnectionNetGraph::add (const db::Net *net, SoftConnectionPinDir dir, const db::Pin *pin, size_t partial_net_count)
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{
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// limiting the partial net count to 1 means we report errors only once in the
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// hierarchy, not on every level
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m_partial_net_count += std::min (size_t (1), partial_net_count);
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m_partial_net_count += partial_net_count;
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// this is where we make the decision about the partial nets ...
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if (! pin && dir == SoftConnectionPinDir::down ()) {
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@ -188,13 +186,13 @@ SoftConnectionInfo::representative_polygon (const db::Net *net, const db::Layout
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return db::DPolygon (bbox);
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}
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void SoftConnectionInfo::report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &net_graph, db::LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<const db::Net *> &seen)
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void SoftConnectionInfo::report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &net_graph, db::LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<std::pair<const db::Net *, db::DCplxTrans> > &seen)
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{
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for (auto cc = net_graph.begin_clusters (); cc != net_graph.end_clusters (); ++cc) {
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const db::Net *net = circuit->net_by_cluster_id (cc->first);
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if (! seen.insert (net).second) {
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if (! seen.insert (std::make_pair (net, trans)).second) {
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continue;
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}
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@ -263,7 +261,7 @@ void SoftConnectionInfo::report (db::LayoutToNetlist &l2n)
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l2n.log_entry (log_entry);
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int index = 0;
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std::set<const db::Net *> seen;
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std::set<std::pair<const db::Net *, db::DCplxTrans> > seen;
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report_partial_nets (c.operator-> (), *sc, l2n, c->name (), db::DCplxTrans (), c->name (), index, seen);
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}
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@ -390,7 +388,13 @@ void SoftConnectionInfo::get_net_connections_through_subcircuit (const db::SubCi
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const SoftConnectionNetGraph *scci = sci.get_net_graph_per_pin (pin);
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if (scci) {
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partial_net_count += scci->partial_net_count ();
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// NOTE: limiting the partial net count here means we do report a partially connected once in the
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// hierarchy, not on every level.
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// Say, if you have two subcircuits, one (A) having 2 partial nets and the other (B) none. Then
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// (A) would be reported to partial nets only and when combining (A) and (B) we just need to check
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// whether B would also have partial nets. By not taking 2 + 0, but 1 + 0 the combination of (A)
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// and (B) does not give an error (error = number of partial nets > 1).
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partial_net_count += std::min (size_t (1), scci->partial_net_count ());
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for (auto p = scci->begin_pins (); p != scci->end_pins (); ++p) {
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if (*p != pin->id ()) {
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@ -344,7 +344,7 @@ private:
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*/
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std::set<size_t> net_connections_through_subcircuits (const db::Net *net, size_t &partial_net_count);
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void report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &cluster_info, LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<const Net *> &seen);
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void report_partial_nets (const db::Circuit *circuit, const SoftConnectionNetGraph &cluster_info, LayoutToNetlist &l2n, const std::string &path, const db::DCplxTrans &trans, const std::string &top_cell, int &index, std::set<std::pair<const db::Net *, db::DCplxTrans> > &seen);
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db::DPolygon representative_polygon (const db::Net *net, const db::LayoutToNetlist &l2n, const db::CplxTrans &trans);
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};
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@ -0,0 +1,13 @@
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* Extracted by KLayout
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.SUBCKT TOP A Q SUBSTRATE
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X$1 \$5 \$1 Q SUBSTRATE INV
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X$2 \$5 A \$1 SUBSTRATE INV
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.ENDS TOP
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.SUBCKT INV \$2 \$4 \$5 SUBSTRATE
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M$1 \$2 \$4 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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M$2 SUBSTRATE \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
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+ PS=3.45U PD=3.45U
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.ENDS INV
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Binary file not shown.
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@ -0,0 +1,93 @@
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$lvs_test_source && source($lvs_test_source)
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if $lvs_test_target_l2n
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report_netlist($lvs_test_target_l2n)
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else
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report_netlist
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end
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writer = write_spice(true, false)
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$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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nplus = input(2, 1)
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pplus = input(2, 2)
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poly = input(3, 0)
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poly_lbl = input(3, 1)
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diff_cont = input(4, 0)
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poly_cont = input(5, 0)
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metal1 = input(6, 0)
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metal1_lbl = input(6, 1)
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via1 = input(7, 0)
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metal2 = input(8, 0)
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metal2_lbl = input(8, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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psd = nil
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nsd = nil
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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ntie = active_in_nwell & nplus
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ptie = active_outside_nwell & pplus
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly })
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# Define connectivity for netlist extraction
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# Inter-layer
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soft_connect(diff_cont, psd)
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soft_connect(diff_cont, nsd)
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soft_connect(diff_cont, ptie)
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soft_connect(diff_cont, ntie)
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soft_connect(ntie, nwell)
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soft_connect(poly_cont, poly)
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connect(diff_cont, metal1)
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connect(poly_cont, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# attach labels
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connect(poly, poly_lbl)
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connect(metal1, metal1_lbl)
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connect(metal2, metal2_lbl)
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# Global
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connect_global(bulk, "SUBSTRATE")
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soft_connect_global(ptie, "SUBSTRATE")
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# Netlist section (NOTE: we only check log here)
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# for debugging: _make_soft_connection_diodes(true)
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netlist
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netlist.simplify
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