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Merge pull request #1491 from KLayout/issue-885

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Issue 885
This commit is contained in:
Matthias Köfferlein
2023-11-07 21:35:04 +01:00
committed by GitHub
parent c71896fc5f 72278b90ec
commit 8d51124fd4
109 changed files with 4676 additions and 1318 deletions
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testdata/algo/device_extract_au14_circuits.gds
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testdata/algo/device_extract_au1_joined_nets.gds
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testdata/algo/device_extract_l14.gds
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testdata/algo/l2n_reader_6.l2n
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@@ -0,0 +1,19 @@
#%l2n-klayout
top(TOP)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
# Mask layer connectivity
# Log entries
message(info description(info))
message(info description(info) cell(cell_name) cat("cat name" "cat description") polygon("(1,1;2,2;3,1)"))
message(warning description(warning))
message(error description(error))
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
testdata/algo/l2n_reader_6s.l2n
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#%l2n-klayout
W(TOP)
U(0.001)
H(I B(info))
H(I B(info) C(cell_name) X("cat name" "cat description") Q("(1,1;2,2;3,1)"))
H(W B(warning))
H(E B(error))
testdata/algo/l2n_reader_au_6.l2n
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@@ -0,0 +1,19 @@
#%l2n-klayout
top(TOP)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
# Mask layer connectivity
# Log entries
message(info description(info))
message(info description(info) cell(cell_name) cat('cat name' 'cat description') polygon('(1,1;2,2;3,1)'))
message(warning description(warning))
message(error description(error))
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
testdata/algo/l2n_writer_au_3.txt
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@@ -0,0 +1,18 @@
#%l2n-klayout
top(TOP)
unit(0.001)
# Layer section
# This section lists the mask layers (drawing or derived) and their connections.
# Mask layers
# Mask layer connectivity
# Log entries
message(info description(info))
message(warning description(warning))
message(error description(error))
# Circuit section
# Circuits are the hierarchical building blocks of the netlist.
testdata/algo/l2n_writer_au_3s.txt
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@@ -0,0 +1,6 @@
#%l2n-klayout
W(TOP)
U(0.001)
H(I B(info))
H(W B(warning))
H(E B(error))
testdata/algo/lvs_test3.lvsdb
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@@ -613,7 +613,17 @@ reference(
# Cross reference
xref(
log(
entry(error description("An error (global)"))
entry(warning description("A warning (global)"))
entry(info description("Some info (global)"))
)
circuit(() INV2PAIRX mismatch
log(
entry(error description("An error"))
entry(warning description("A warning"))
entry(info description("Some info"))
)
kk( jj("hello" W) jj("world!" E) ) # invalid
xref(
)
@@ -684,4 +694,5 @@ xref(
circuit(5 5 match)
)
)
kk( xx(1 2 3) ) # invalid
)
testdata/algo/lvs_test3_au.lvsdb
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@@ -602,7 +602,17 @@ reference(
# Cross reference
xref(
log(
entry(error description('An error (global)'))
entry(warning description('A warning (global)'))
entry(info description('Some info (global)'))
)
circuit(() INV2PAIRX mismatch
log(
entry(error description('An error'))
entry(warning description('A warning'))
entry(info description('Some info'))
)
xref(
)
)
testdata/drc/drcSimpleTests_12.drc
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@@ -21,8 +21,8 @@ metal2_lbl = input(8, 1)
# Computed layers
pactive = active & nwell
pgate = active & poly
psd = active - pgate
pgate = pactive & poly
psd = pactive - pgate
nactive = active - nwell
ngate = nactive & poly
testdata/drc/drcSimpleTests_au12a.cir
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+14 -18
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@@ -5,12 +5,12 @@
* net 1 FB
* net 2 OSC
* net 3 NEXT
* net 4 VSSZ,VSS
* net 5 VDDZ,VDD
* cell instance $1 r180 *1 -0.24,9.18
X$1 16 1 2 4 5 INV2
* cell instance $2 r0 *1 0,0
X$2 1 14 15 4 5 INV2
* net 4 VSSZ
* net 5 VDDZ
* cell instance $1 r0 *1 0,0
X$1 1 14 15 4 5 INV2
* cell instance $2 r180 *1 -0.24,9.18
X$2 16 1 2 4 5 INV2
* cell instance $3 r180 *1 10.32,9.18
X$3 3 9 19 4 5 INV2
* cell instance $4 r0 *1 10.56,0
@@ -46,18 +46,14 @@ X$2 2 5 1 TRANS
X$3 5 3 2 TRANS
* cell instance $4 m0 *1 0.4,0
X$4 4 3 2 TRANS
* device instance $1 -0.4,0 PMOS
M$1 2 1 4 2 PMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $2 0.4,0 PMOS
M$2 4 2 3 4 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $3 -0.4,2.8 PMOS
M$3 2 1 5 2 PMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $4 0.4,2.8 PMOS
M$4 5 2 3 5 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $5 -0.4,0 NMOS
M$5 2 1 4 2 NMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $6 0.4,0 NMOS
M$6 4 2 3 4 NMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $1 r0 *1 -0.4,2.8 PMOS
M$1 5 1 2 2 PMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $2 r0 *1 0.4,2.8 PMOS
M$2 3 2 5 5 PMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
* device instance $3 r0 *1 -0.4,0 NMOS
M$3 4 1 2 2 NMOS L=0.25U W=0.95U AS=0.49875P AD=0.26125P PS=2.95U PD=1.5U
* device instance $4 r0 *1 0.4,0 NMOS
M$4 3 2 4 4 NMOS L=0.25U W=0.95U AS=0.26125P AD=0.49875P PS=1.5U PD=2.95U
.ENDS INV2
* cell TRANS
testdata/drc/implicit_nets.gds
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testdata/lvs/bbdevices3b.lvsdb
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@@ -280,6 +280,9 @@ reference(
# Cross reference
xref(
log(
entry(error description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n B: BWBTEST'))
)
circuit(BBGATEST BBGATEST match
xref(
pin(() 1 match)
testdata/lvs/bbdevices4b.lvsdb
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@@ -275,6 +275,9 @@ reference(
# Cross reference
xref(
log(
entry(error description('Circuits testall and TESTALL could not be compared because the following subcircuits failed to compare:\n B: BWBTEST'))
)
circuit(BBGATEST BBGATEST match
xref(
pin(() 1 match)
testdata/lvs/double_height2.lvs
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@@ -3,6 +3,8 @@ source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb)
ignore_extraction_errors(true)
writer = write_spice(true, false)
target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
testdata/lvs/double_height2.lvsdb
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@@ -27,6 +27,9 @@ J(
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets GND must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
H(W B('Must-connect nets R must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
H(E B('Must-connect nets R of circuit INV2 are not connected') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
K(PMOS MOS3)
K(NMOS MOS3)
D(D$PMOS PMOS
testdata/lvs/double_height2_texts.lvs
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@@ -3,6 +3,8 @@ source($lvs_test_source)
report_lvs($lvs_test_target_lvsdb)
ignore_extraction_errors(true)
writer = write_spice(true, false)
target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
testdata/lvs/double_height2_texts.lvsdb
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@@ -27,6 +27,9 @@ J(
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets GND must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
H(W B('Must-connect nets R must be connected further up in the hierarchy - this is an error at chip top level') C(INVCHAIN) X('must-connect'))
H(E B('Must-connect nets R of circuit INV2 are not connected') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
K(PMOS MOS3)
K(NMOS MOS3)
D(D$PMOS PMOS
testdata/lvs/must_connect1.cir
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* Extracted by KLayout
.SUBCKT TOP VSSTOP A Q
X$1 \$8 \$2 \$1 \$1 Q VSSTOP INV2
X$2 A \$3 VSSTOP \$3 \$2 \$8 INVCHAIN
.ENDS TOP
.SUBCKT INVCHAIN IN IN2 VSS|VSS2|VSS2B OUT OUT2 VDD
X$1 VDD IN2 \$1 \$1 OUT2 VSS|VSS2|VSS2B INV2
X$2 VDD IN \$2 \$2 OUT VSS|VSS2|VSS2B INV2
.ENDS INVCHAIN
.SUBCKT INV2 VDD A1 A2 Q1 Q2 VSS
X$1 VSS VDD A2 Q2 INV
X$2 VSS VDD A1 Q1 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV
testdata/lvs/must_connect1.gds
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testdata/lvs/must_connect1.lvs
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$lvs_test_source && source($lvs_test_source)
if $lvs_test_target_lvsdb
report_lvs($lvs_test_target_lvsdb)
else
report_lvs
end
writer = write_spice(true, false)
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
# needs this delegate because we use MOS3 which is not available in Spice
class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
# says we want to catch these subcircuits as devices
def wants_subcircuit(name)
name == "HVNMOS" || name == "HVPMOS"
end
# translate the element
def element(circuit, el, name, model, value, nets, params)
if el != "M"
# all other elements are left to the standard implementation
return super
end
if nets.size != 4
error("Device #{model} needs four nodes")
end
# provide a device class
cls = circuit.netlist.device_class_by_name(model)
if ! cls
cls = RBA::DeviceClassMOS3Transistor::new
cls.name = model
circuit.netlist.add(cls)
end
# create a device
device = circuit.create_device(cls, name)
# and configure the device
[ "S", "G", "D" ].each_with_index do |t,index|
device.connect_terminal(t, nets[index])
end
device.set_parameter("W", params["W"] * 1e6)
device.set_parameter("L", params["L"] * 1e6)
device
end
end
reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
schematic(File.basename(source.path, ".*") + ".sch", reader)
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
poly = input(3, 0)
poly_lbl = input(3, 1)
diff_cont = input(4, 0)
poly_cont = input(5, 0)
metal1 = input(6, 0)
metal1_lbl = input(6, 1)
via1 = input(7, 0)
metal2 = input(8, 0)
metal2_lbl = input(8, 1)
# Bulk layer for terminal provisioning
bulk = polygon_layer
psd = nil
nsd = nil
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell
pgate = pactive & poly
psd = pactive - pgate
active_outside_nwell = active - nwell
nactive = active_outside_nwell
ngate = nactive & poly
nsd = nactive - ngate
# Device extraction
# PMOS transistor device extraction
extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate,
"tS" => psd, "tD" => psd, "tG" => poly })
# NMOS transistor device extraction
extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate,
"tS" => nsd, "tD" => nsd, "tG" => poly })
# Define connectivity for netlist extraction
# Inter-layer
connect(psd, diff_cont)
connect(nsd, diff_cont)
connect(poly, poly_cont)
connect(diff_cont, metal1)
connect(poly_cont, metal1)
connect(metal1, via1)
connect(via1, metal2)
# attach labels
connect(poly, poly_lbl)
connect(metal1, metal1_lbl)
connect(metal2, metal2_lbl)
# Global
connect_global(bulk, "SUBSTRATE")
# Implicit connection of the INV2
# VSS nets
connect_implicit("INV2", "VSS")
connect_implicit("TOP", "VSS*")
# Fix 1
connect_explicit("INVCHAIN", ["VSS2", "VSS2B", "VSS"])
connect_implicit("INVCHAIN", "VDD")
# Compare section
netlist.simplify
align
compare
testdata/lvs/must_connect1.lvsdb
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#%lvsdb-klayout
J(
W(TOP)
U(0.001)
L(l3 '3/0')
L(l11 '3/1')
L(l6 '4/0')
L(l7 '5/0')
L(l8 '6/0')
L(l12 '6/1')
L(l9 '7/0')
L(l10 '8/0')
L(l13 '8/1')
L(l14)
L(l2)
L(l5)
C(l3 l3 l11 l7)
C(l11 l3 l11)
C(l6 l6 l8 l2 l5)
C(l7 l3 l7 l8)
C(l8 l6 l7 l8 l12 l9)
C(l12 l8 l12)
C(l9 l8 l9 l10)
C(l10 l9 l10 l13)
C(l13 l10 l13)
C(l14 l14)
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets VSSTOP must be connected further up in the hierarchy - this is an error at chip top level') C(TOP) X('must-connect'))
K(PMOS MOS3)
K(NMOS MOS3)
D(D$PMOS PMOS
T(S
R(l2 (-900 -475) (775 950))
)
T(G
R(l3 (-125 -475) (250 950))
)
T(D
R(l2 (125 -475) (775 950))
)
)
D(D$NMOS NMOS
T(S
R(l5 (-900 -475) (775 950))
)
T(G
R(l3 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (775 950))
)
)
X(INV
R((-1500 -800) (3000 4600))
N(1
R(l6 (290 -310) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -690) (360 760))
R(l9 (-305 -705) (250 250))
R(l9 (-250 150) (250 250))
R(l10 (-2025 -775) (3000 900))
R(l5 (-1375 -925) (775 950))
)
N(2
R(l6 (290 2490) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -690) (360 760))
R(l9 (-305 -705) (250 250))
R(l9 (-250 150) (250 250))
R(l10 (-2025 -775) (3000 900))
R(l2 (-1375 -925) (775 950))
)
N(3
R(l3 (-125 -250) (250 2500))
R(l3 (-250 -3050) (250 1600))
R(l3 (-250 1200) (250 1600))
)
N(4
R(l6 (-510 -310) (220 220))
R(l6 (-220 180) (220 220))
R(l6 (-220 2180) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -3530) (360 2840))
R(l8 (-360 -2800) (360 760))
R(l8 (-360 2040) (360 760))
R(l2 (-680 -855) (775 950))
R(l5 (-775 -3750) (775 950))
)
P(1)
P(2)
P(3)
P(4)
D(1 D$PMOS
Y(0 2800)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 4)
T(G 3)
T(D 2)
)
D(2 D$NMOS
Y(0 0)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 4)
T(G 3)
T(D 1)
)
)
X(INV2
R((0 0) (3000 9200))
N(1 I(VDD)
R(l10 (0 3150) (3000 2900))
R(l13 (-1890 -1450) (0 0))
)
N(2 I(A1)
R(l11 (1480 7110) (0 0))
)
N(3 I(A2)
R(l11 (1520 1950) (0 0))
)
N(4 I(Q1)
R(l12 (1920 7070) (0 0))
)
N(5 I(Q2)
R(l12 (1940 1950) (0 0))
)
N(6 I(VSS)
R(l13 (2680 8390) (0 0))
R(l13 (-30 -7640) (0 0))
)
P(1 I(VDD))
P(2 I(A1))
P(3 I(A2))
P(4 I(Q1))
P(5 I(Q2))
P(6 I(VSS))
X(1 INV M O(180) Y(1500 800)
P(0 6)
P(1 1)
P(2 3)
P(3 5)
)
X(2 INV O(180) Y(1500 8400)
P(0 6)
P(1 1)
P(2 2)
P(3 4)
)
)
X(INVCHAIN
R((-915 -15) (10415 9215))
N(1
R(l3 (7340 1650) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(2
R(l3 (1625 1835) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(3 I(IN)
R(l3 (-90 6850) (1590 650))
R(l11 (-700 -350) (0 0))
)
N(4 I(IN2)
R(l3 (5665 6790) (1590 650))
R(l11 (-700 -350) (0 0))
)
N(5 I('VSS,VSS2,VSS2B')
R(l10 (-915 675) (915 250))
R(l10 (-915 0) (250 7325))
R(l10 (-250 0) (915 250))
R(l13 (-510 -125) (0 0))
R(l13 (8990 -255) (0 0))
R(l13 (25 -7115) (0 0))
)
N(6 I(OUT)
R(l12 (1890 2105) (0 0))
)
N(7 I(OUT2)
R(l12 (7730 2155) (0 0))
)
N(8 I(VDD)
R(l13 (8035 4540) (0 0))
R(l13 (-5735 60) (0 0))
)
P(3 I(IN))
P(4 I(IN2))
P(5 I('VSS,VSS2,VSS2B'))
P(6 I(OUT))
P(7 I(OUT2))
P(8 I(VDD))
X(1 INV2 Y(5780 -15)
P(0 8)
P(1 4)
P(2 1)
P(3 1)
P(4 7)
P(5 5)
)
X(2 INV2 Y(0 0)
P(0 8)
P(1 3)
P(2 2)
P(3 2)
P(4 6)
P(5 5)
)
)
X(TOP
R((-305 350) (15415 9225))
N(1
R(l3 (12950 2130) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(2
R(l3 (12100 7300) (640 530))
R(l7 (-540 -415) (270 250))
R(l8 (-1695 -250) (1695 250))
R(l8 (-4075 -5650) (2630 250))
R(l8 (-250 0) (250 5150))
)
N(3
R(l7 (6465 7325) (220 240))
R(l8 (-4100 -5365) (3125 250))
R(l8 (-250 0) (250 4860))
R(l8 (-250 0) (1225 250))
)
N(4 I(VSSTOP)
R(l10 (3610 8300) (2815 440))
R(l10 (-710 -250) (0 0))
R(l10 (3675 -165) (1975 565))
R(l10 (-1975 -8190) (1975 575))
R(l10 (-1005 -255) (0 0))
)
N(5 I(A)
R(l11 (975 7530) (0 0))
)
N(6 I(Q)
R(l12 (13260 2010) (0 0))
)
N(7
R(l10 (3450 4840) (3055 250))
R(l10 (2885 -250) (1975 250))
)
P(4 I(VSSTOP))
P(5 I(A))
P(6 I(Q))
X(1 INV2 Y(11365 375)
P(0 7)
P(1 2)
P(2 1)
P(3 1)
P(4 6)
P(5 4)
)
X(2 INVCHAIN Y(610 365)
P(0 5)
P(1 3)
P(2 4)
P(3 3)
P(4 2)
P(5 7)
)
)
)
H(
K(PMOS MOS3)
K(NMOS MOS3)
X(INV
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A))
N(4 I(Q))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A))
P(4 I(Q))
D(1 PMOS
I($1)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 1)
T(G 3)
T(D 4)
)
D(2 NMOS
I($3)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(G 3)
T(D 4)
)
)
X(INV2
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A1))
N(4 I(Q1))
N(5 I(A2))
N(6 I(Q2))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A1))
P(4 I(Q1))
P(5 I(A2))
P(6 I(Q2))
X(1 INV I($1)
P(0 1)
P(1 2)
P(2 3)
P(3 4)
)
X(2 INV I($2)
P(0 1)
P(1 2)
P(2 5)
P(3 6)
)
)
X(INVCHAIN
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A1))
N(4 I(Q1))
N(5 I(A2))
N(6 I(Q2))
N(7 I('1'))
N(8 I('2'))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A1))
P(4 I(Q1))
P(5 I(A2))
P(6 I(Q2))
X(1 INV2 I($2)
P(0 1)
P(1 2)
P(2 3)
P(3 7)
P(4 7)
P(5 4)
)
X(2 INV2 I($3)
P(0 1)
P(1 2)
P(2 5)
P(3 8)
P(4 8)
P(5 6)
)
)
X(TOP
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A))
N(4 I('1'))
N(5 I('3'))
N(6 I('2'))
N(7 I(Q))
X(1 INVCHAIN I($1)
P(0 1)
P(1 2)
P(2 3)
P(3 4)
P(4 4)
P(5 5)
)
X(2 INV2 I($2)
P(0 1)
P(1 2)
P(2 5)
P(3 6)
P(4 6)
P(5 7)
)
)
)
Z(
X(INV INV 1
Z(
N(3 3 1)
N(4 4 1)
N(2 1 1)
N(1 2 1)
P(2 2 1)
P(3 3 1)
P(1 0 1)
P(0 1 1)
D(2 2 1)
D(1 1 1)
)
)
X(INV2 INV2 1
Z(
N(2 3 1)
N(3 5 1)
N(4 4 1)
N(5 6 1)
N(1 1 1)
N(6 2 1)
P(1 2 1)
P(2 4 1)
P(3 3 1)
P(4 5 1)
P(0 0 1)
P(5 1 1)
X(2 1 1)
X(1 2 1)
)
)
X(INVCHAIN INVCHAIN 1
L(
M(W B('Matching nets OUT vs. Q1 from an ambiguous group of nets'))
M(W B('Matching nets OUT2 vs. Q2 from an ambiguous group of nets'))
M(I B('Matching nets $2 vs. 1 following an ambiguous match'))
M(I B('Matching nets IN vs. A1 following an ambiguous match'))
M(I B('Matching nets $1 vs. 2 following an ambiguous match'))
M(I B('Matching nets IN2 vs. A2 following an ambiguous match'))
)
Z(
N(2 7 1)
N(1 8 1)
N(3 3 1)
N(4 5 1)
N(6 4 W)
N(7 6 W)
N(8 1 1)
N(5 2 1)
P(0 2 1)
P(1 4 1)
P(3 3 1)
P(4 5 1)
P(5 0 1)
P(2 1 1)
X(2 1 1)
X(1 2 1)
)
)
X(TOP TOP 1
Z(
N(3 4 1)
N(1 6 1)
N(2 5 1)
N(7 1 1)
N(5 3 1)
N(6 7 1)
N(4 2 1)
P(1 () 1)
P(2 () 1)
P(0 () 1)
X(1 2 1)
X(2 1 1)
)
)
)
testdata/lvs/must_connect1.sch
Vendored
+24
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@@ -0,0 +1,24 @@
.SUBCKT TOP
X$1 VDD VSS A 1 1 3 INVCHAIN
X$2 VDD VSS 3 2 2 Q INV2
.ENDS TOP
* cell INVCHAIN
.SUBCKT INVCHAIN VDD VSS A1 Q1 A2 Q2
X$2 VDD VSS A1 1 1 Q1 INV2
X$3 VDD VSS A2 2 2 Q2 INV2
.ENDS INVCHAIN
* cell INV2
.SUBCKT INV2 VDD VSS A1 Q1 A2 Q2
X$1 VDD VSS A1 Q1 INV
X$2 VDD VSS A2 Q2 INV
.ENDS INV2
* cell INV
.SUBCKT INV VDD VSS A Q
M$1 VDD A Q VDD PMOS L=0.25U W=0.95U
M$3 VSS A Q VSS NMOS L=0.25U W=0.95U
.ENDS INV
testdata/lvs/must_connect1_tl.cir
Vendored
+23
View File
@@ -0,0 +1,23 @@
* Extracted by KLayout
.SUBCKT TOP VSSTOP A Q
X$1 \$8 \$2 \$1 \$1 Q VSSTOP INV2
X$2 A \$3 VSSTOP \$3 \$2 \$8 INVCHAIN
.ENDS TOP
.SUBCKT INVCHAIN IN IN2 VSS|VSS2|VSS2B OUT OUT2 VDD
X$1 VDD IN2 \$1 \$1 OUT2 VSS|VSS2|VSS2B INV2
X$2 VDD IN \$2 \$2 OUT VSS|VSS2|VSS2B INV2
.ENDS INVCHAIN
.SUBCKT INV2 VDD A1 A2 Q1 Q2 VSS
X$1 VSS VDD A2 Q2 INV
X$2 VSS VDD A1 Q1 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV
testdata/lvs/must_connect1_tl.lvs
Vendored
+143
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@@ -0,0 +1,143 @@
$lvs_test_source && source($lvs_test_source)
if $lvs_test_target_lvsdb
report_lvs($lvs_test_target_lvsdb)
else
report_lvs
end
writer = write_spice(true, false)
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
# Turns the warning about VSSTOP into an error
top_level(true)
ignore_extraction_errors(true)
# needs this delegate because we use MOS3 which is not available in Spice
class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
# says we want to catch these subcircuits as devices
def wants_subcircuit(name)
name == "HVNMOS" || name == "HVPMOS"
end
# translate the element
def element(circuit, el, name, model, value, nets, params)
if el != "M"
# all other elements are left to the standard implementation
return super
end
if nets.size != 4
error("Device #{model} needs four nodes")
end
# provide a device class
cls = circuit.netlist.device_class_by_name(model)
if ! cls
cls = RBA::DeviceClassMOS3Transistor::new
cls.name = model
circuit.netlist.add(cls)
end
# create a device
device = circuit.create_device(cls, name)
# and configure the device
[ "S", "G", "D" ].each_with_index do |t,index|
device.connect_terminal(t, nets[index])
end
device.set_parameter("W", params["W"] * 1e6)
device.set_parameter("L", params["L"] * 1e6)
device
end
end
reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
schematic(File.basename(source.path, ".*") + ".sch", reader)
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
poly = input(3, 0)
poly_lbl = input(3, 1)
diff_cont = input(4, 0)
poly_cont = input(5, 0)
metal1 = input(6, 0)
metal1_lbl = input(6, 1)
via1 = input(7, 0)
metal2 = input(8, 0)
metal2_lbl = input(8, 1)
# Bulk layer for terminal provisioning
bulk = polygon_layer
psd = nil
nsd = nil
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell
pgate = pactive & poly
psd = pactive - pgate
active_outside_nwell = active - nwell
nactive = active_outside_nwell
ngate = nactive & poly
nsd = nactive - ngate
# Device extraction
# PMOS transistor device extraction
extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate,
"tS" => psd, "tD" => psd, "tG" => poly })
# NMOS transistor device extraction
extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate,
"tS" => nsd, "tD" => nsd, "tG" => poly })
# Define connectivity for netlist extraction
# Inter-layer
connect(psd, diff_cont)
connect(nsd, diff_cont)
connect(poly, poly_cont)
connect(diff_cont, metal1)
connect(poly_cont, metal1)
connect(metal1, via1)
connect(via1, metal2)
# attach labels
connect(poly, poly_lbl)
connect(metal1, metal1_lbl)
connect(metal2, metal2_lbl)
# Global
connect_global(bulk, "SUBSTRATE")
# Implicit connection of the INV2
# VSS nets
connect_implicit("INV2", "VSS")
connect_implicit("TOP", "VSS*")
# Fix 1
connect_explicit("INVCHAIN", ["VSS2", "VSS2B", "VSS"])
connect_implicit("INVCHAIN", "VDD")
# Compare section
netlist.simplify
align
compare
testdata/lvs/must_connect1_tl.lvsdb
Vendored
+484
View File
@@ -0,0 +1,484 @@
#%lvsdb-klayout
J(
W(TOP)
U(0.001)
L(l3 '3/0')
L(l11 '3/1')
L(l6 '4/0')
L(l7 '5/0')
L(l8 '6/0')
L(l12 '6/1')
L(l9 '7/0')
L(l10 '8/0')
L(l13 '8/1')
L(l14)
L(l2)
L(l5)
C(l3 l3 l11 l7)
C(l11 l3 l11)
C(l6 l6 l8 l2 l5)
C(l7 l3 l7 l8)
C(l8 l6 l7 l8 l12 l9)
C(l12 l8 l12)
C(l9 l8 l9 l10)
C(l10 l9 l10 l13)
C(l13 l10 l13)
C(l14 l14)
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(E B('Must-connect nets VSSTOP must be connected further up in the hierarchy - this is an error at chip top level') C(TOP) X('must-connect'))
K(PMOS MOS3)
K(NMOS MOS3)
D(D$PMOS PMOS
T(S
R(l2 (-900 -475) (775 950))
)
T(G
R(l3 (-125 -475) (250 950))
)
T(D
R(l2 (125 -475) (775 950))
)
)
D(D$NMOS NMOS
T(S
R(l5 (-900 -475) (775 950))
)
T(G
R(l3 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (775 950))
)
)
X(INV
R((-1500 -800) (3000 4600))
N(1
R(l6 (290 -310) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -690) (360 760))
R(l9 (-305 -705) (250 250))
R(l9 (-250 150) (250 250))
R(l10 (-2025 -775) (3000 900))
R(l5 (-1375 -925) (775 950))
)
N(2
R(l6 (290 2490) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -690) (360 760))
R(l9 (-305 -705) (250 250))
R(l9 (-250 150) (250 250))
R(l10 (-2025 -775) (3000 900))
R(l2 (-1375 -925) (775 950))
)
N(3
R(l3 (-125 -250) (250 2500))
R(l3 (-250 -3050) (250 1600))
R(l3 (-250 1200) (250 1600))
)
N(4
R(l6 (-510 -310) (220 220))
R(l6 (-220 180) (220 220))
R(l6 (-220 2180) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -3530) (360 2840))
R(l8 (-360 -2800) (360 760))
R(l8 (-360 2040) (360 760))
R(l2 (-680 -855) (775 950))
R(l5 (-775 -3750) (775 950))
)
P(1)
P(2)
P(3)
P(4)
D(1 D$PMOS
Y(0 2800)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 4)
T(G 3)
T(D 2)
)
D(2 D$NMOS
Y(0 0)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 4)
T(G 3)
T(D 1)
)
)
X(INV2
R((0 0) (3000 9200))
N(1 I(VDD)
R(l10 (0 3150) (3000 2900))
R(l13 (-1890 -1450) (0 0))
)
N(2 I(A1)
R(l11 (1480 7110) (0 0))
)
N(3 I(A2)
R(l11 (1520 1950) (0 0))
)
N(4 I(Q1)
R(l12 (1920 7070) (0 0))
)
N(5 I(Q2)
R(l12 (1940 1950) (0 0))
)
N(6 I(VSS)
R(l13 (2680 8390) (0 0))
R(l13 (-30 -7640) (0 0))
)
P(1 I(VDD))
P(2 I(A1))
P(3 I(A2))
P(4 I(Q1))
P(5 I(Q2))
P(6 I(VSS))
X(1 INV M O(180) Y(1500 800)
P(0 6)
P(1 1)
P(2 3)
P(3 5)
)
X(2 INV O(180) Y(1500 8400)
P(0 6)
P(1 1)
P(2 2)
P(3 4)
)
)
X(INVCHAIN
R((-915 -15) (10415 9215))
N(1
R(l3 (7340 1650) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(2
R(l3 (1625 1835) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(3 I(IN)
R(l3 (-90 6850) (1590 650))
R(l11 (-700 -350) (0 0))
)
N(4 I(IN2)
R(l3 (5665 6790) (1590 650))
R(l11 (-700 -350) (0 0))
)
N(5 I('VSS,VSS2,VSS2B')
R(l10 (-915 675) (915 250))
R(l10 (-915 0) (250 7325))
R(l10 (-250 0) (915 250))
R(l13 (-510 -125) (0 0))
R(l13 (8990 -255) (0 0))
R(l13 (25 -7115) (0 0))
)
N(6 I(OUT)
R(l12 (1890 2105) (0 0))
)
N(7 I(OUT2)
R(l12 (7730 2155) (0 0))
)
N(8 I(VDD)
R(l13 (8035 4540) (0 0))
R(l13 (-5735 60) (0 0))
)
P(3 I(IN))
P(4 I(IN2))
P(5 I('VSS,VSS2,VSS2B'))
P(6 I(OUT))
P(7 I(OUT2))
P(8 I(VDD))
X(1 INV2 Y(5780 -15)
P(0 8)
P(1 4)
P(2 1)
P(3 1)
P(4 7)
P(5 5)
)
X(2 INV2 Y(0 0)
P(0 8)
P(1 3)
P(2 2)
P(3 2)
P(4 6)
P(5 5)
)
)
X(TOP
R((-305 350) (15415 9225))
N(1
R(l3 (12950 2130) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(2
R(l3 (12100 7300) (640 530))
R(l7 (-540 -415) (270 250))
R(l8 (-1695 -250) (1695 250))
R(l8 (-4075 -5650) (2630 250))
R(l8 (-250 0) (250 5150))
)
N(3
R(l7 (6465 7325) (220 240))
R(l8 (-4100 -5365) (3125 250))
R(l8 (-250 0) (250 4860))
R(l8 (-250 0) (1225 250))
)
N(4 I(VSSTOP)
R(l10 (3610 8300) (2815 440))
R(l10 (-710 -250) (0 0))
R(l10 (3675 -165) (1975 565))
R(l10 (-1975 -8190) (1975 575))
R(l10 (-1005 -255) (0 0))
)
N(5 I(A)
R(l11 (975 7530) (0 0))
)
N(6 I(Q)
R(l12 (13260 2010) (0 0))
)
N(7
R(l10 (3450 4840) (3055 250))
R(l10 (2885 -250) (1975 250))
)
P(4 I(VSSTOP))
P(5 I(A))
P(6 I(Q))
X(1 INV2 Y(11365 375)
P(0 7)
P(1 2)
P(2 1)
P(3 1)
P(4 6)
P(5 4)
)
X(2 INVCHAIN Y(610 365)
P(0 5)
P(1 3)
P(2 4)
P(3 3)
P(4 2)
P(5 7)
)
)
)
H(
K(PMOS MOS3)
K(NMOS MOS3)
X(INV
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A))
N(4 I(Q))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A))
P(4 I(Q))
D(1 PMOS
I($1)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 1)
T(G 3)
T(D 4)
)
D(2 NMOS
I($3)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(G 3)
T(D 4)
)
)
X(INV2
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A1))
N(4 I(Q1))
N(5 I(A2))
N(6 I(Q2))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A1))
P(4 I(Q1))
P(5 I(A2))
P(6 I(Q2))
X(1 INV I($1)
P(0 1)
P(1 2)
P(2 3)
P(3 4)
)
X(2 INV I($2)
P(0 1)
P(1 2)
P(2 5)
P(3 6)
)
)
X(INVCHAIN
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A1))
N(4 I(Q1))
N(5 I(A2))
N(6 I(Q2))
N(7 I('1'))
N(8 I('2'))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A1))
P(4 I(Q1))
P(5 I(A2))
P(6 I(Q2))
X(1 INV2 I($2)
P(0 1)
P(1 2)
P(2 3)
P(3 7)
P(4 7)
P(5 4)
)
X(2 INV2 I($3)
P(0 1)
P(1 2)
P(2 5)
P(3 8)
P(4 8)
P(5 6)
)
)
X(TOP
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A))
N(4 I('1'))
N(5 I('3'))
N(6 I('2'))
N(7 I(Q))
X(1 INVCHAIN I($1)
P(0 1)
P(1 2)
P(2 3)
P(3 4)
P(4 4)
P(5 5)
)
X(2 INV2 I($2)
P(0 1)
P(1 2)
P(2 5)
P(3 6)
P(4 6)
P(5 7)
)
)
)
Z(
X(INV INV 1
Z(
N(3 3 1)
N(4 4 1)
N(2 1 1)
N(1 2 1)
P(2 2 1)
P(3 3 1)
P(1 0 1)
P(0 1 1)
D(2 2 1)
D(1 1 1)
)
)
X(INV2 INV2 1
Z(
N(2 3 1)
N(3 5 1)
N(4 4 1)
N(5 6 1)
N(1 1 1)
N(6 2 1)
P(1 2 1)
P(2 4 1)
P(3 3 1)
P(4 5 1)
P(0 0 1)
P(5 1 1)
X(2 1 1)
X(1 2 1)
)
)
X(INVCHAIN INVCHAIN 1
L(
M(W B('Matching nets OUT vs. Q1 from an ambiguous group of nets'))
M(W B('Matching nets OUT2 vs. Q2 from an ambiguous group of nets'))
M(I B('Matching nets $2 vs. 1 following an ambiguous match'))
M(I B('Matching nets IN vs. A1 following an ambiguous match'))
M(I B('Matching nets $1 vs. 2 following an ambiguous match'))
M(I B('Matching nets IN2 vs. A2 following an ambiguous match'))
)
Z(
N(2 7 1)
N(1 8 1)
N(3 3 1)
N(4 5 1)
N(6 4 W)
N(7 6 W)
N(8 1 1)
N(5 2 1)
P(0 2 1)
P(1 4 1)
P(3 3 1)
P(4 5 1)
P(5 0 1)
P(2 1 1)
X(2 1 1)
X(1 2 1)
)
)
X(TOP TOP 1
Z(
N(3 4 1)
N(1 6 1)
N(2 5 1)
N(7 1 1)
N(5 3 1)
N(6 7 1)
N(4 2 1)
P(1 () 1)
P(2 () 1)
P(0 () 1)
X(1 2 1)
X(2 1 1)
)
)
)
testdata/lvs/must_connect2.cir
Vendored
+23
View File
@@ -0,0 +1,23 @@
* Extracted by KLayout
.SUBCKT TOP VSSTOP A Q VDD
X$1 VDD \$2 \$1 \$1 Q VSSTOP INV2
X$2 A \$3 VSSTOP \$3 \$2 VDD INVCHAIN
.ENDS TOP
.SUBCKT INVCHAIN IN IN2 VSS|VSS2|VSS2B OUT OUT2 VDD
X$1 VDD IN2 \$1 \$1 OUT2 VSS|VSS2|VSS2B INV2
X$2 VDD IN \$2 \$2 OUT VSS|VSS2|VSS2B INV2
.ENDS INVCHAIN
.SUBCKT INV2 VDD A1 A2 Q1 Q2 VSS
X$1 VSS VDD A2 Q2 INV
X$2 VSS VDD A1 Q1 INV
.ENDS INV2
.SUBCKT INV \$1 \$2 \$3 \$4
M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
+ PD=3.45U
.ENDS INV
testdata/lvs/must_connect2.gds
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BIN
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testdata/lvs/must_connect2.lvs
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+142
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@@ -0,0 +1,142 @@
$lvs_test_source && source($lvs_test_source)
if $lvs_test_target_lvsdb
report_lvs($lvs_test_target_lvsdb)
else
report_lvs
end
# Implicit connection of the INV2
# VSS nets
connect_implicit("INV2", "VSS")
connect_implicit("TOP", "VSS*")
# Fix 1
connect_explicit("INVCHAIN", ["VSS2", "VSS2B", "VSS"])
connect_implicit("INVCHAIN", "VDD")
connect_explicit("TOP", ["VDD"])
ignore_extraction_errors(true)
writer = write_spice(true, false)
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
# needs this delegate because we use MOS3 which is not available in Spice
class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
# says we want to catch these subcircuits as devices
def wants_subcircuit(name)
name == "HVNMOS" || name == "HVPMOS"
end
# translate the element
def element(circuit, el, name, model, value, nets, params)
if el != "M"
# all other elements are left to the standard implementation
return super
end
if nets.size != 4
error("Device #{model} needs four nodes")
end
# provide a device class
cls = circuit.netlist.device_class_by_name(model)
if ! cls
cls = RBA::DeviceClassMOS3Transistor::new
cls.name = model
circuit.netlist.add(cls)
end
# create a device
device = circuit.create_device(cls, name)
# and configure the device
[ "S", "G", "D" ].each_with_index do |t,index|
device.connect_terminal(t, nets[index])
end
device.set_parameter("W", params["W"] * 1e6)
device.set_parameter("L", params["L"] * 1e6)
device
end
end
reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
schematic(File.basename(source.path, ".*") + ".sch", reader)
deep
# Drawing layers
nwell = input(1, 0)
active = input(2, 0)
poly = input(3, 0)
poly_lbl = input(3, 1)
diff_cont = input(4, 0)
poly_cont = input(5, 0)
metal1 = input(6, 0)
metal1_lbl = input(6, 1)
via1 = input(7, 0)
metal2 = input(8, 0)
metal2_lbl = input(8, 1)
# Bulk layer for terminal provisioning
bulk = polygon_layer
psd = nil
nsd = nil
# Computed layers
active_in_nwell = active & nwell
pactive = active_in_nwell
pgate = pactive & poly
psd = pactive - pgate
active_outside_nwell = active - nwell
nactive = active_outside_nwell
ngate = nactive & poly
nsd = nactive - ngate
# Device extraction
# PMOS transistor device extraction
extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate,
"tS" => psd, "tD" => psd, "tG" => poly })
# NMOS transistor device extraction
extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate,
"tS" => nsd, "tD" => nsd, "tG" => poly })
# Define connectivity for netlist extraction
# Inter-layer
connect(psd, diff_cont)
connect(nsd, diff_cont)
connect(poly, poly_cont)
connect(diff_cont, metal1)
connect(poly_cont, metal1)
connect(metal1, via1)
connect(via1, metal2)
# attach labels
connect(poly, poly_lbl)
connect(metal1, metal1_lbl)
connect(metal2, metal2_lbl)
# Global
connect_global(bulk, "SUBSTRATE")
# Compare section
netlist.simplify
align
# Skip as we have errors ..
compare
testdata/lvs/must_connect2.lvsdb
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#%lvsdb-klayout
J(
W(TOP)
U(0.001)
L(l3 '3/0')
L(l11 '3/1')
L(l6 '4/0')
L(l7 '5/0')
L(l8 '6/0')
L(l12 '6/1')
L(l9 '7/0')
L(l10 '8/0')
L(l13 '8/1')
L(l14)
L(l2)
L(l5)
C(l3 l3 l11 l7)
C(l11 l3 l11)
C(l6 l6 l8 l2 l5)
C(l7 l3 l7 l8)
C(l8 l6 l7 l8 l12 l9)
C(l12 l8 l12)
C(l9 l8 l9 l10)
C(l10 l9 l10 l13)
C(l13 l10 l13)
C(l14 l14)
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets VSSTOP must be connected further up in the hierarchy - this is an error at chip top level') C(TOP) X('must-connect'))
H(W B('Must-connect nets VDD must be connected further up in the hierarchy - this is an error at chip top level') C(TOP) X('must-connect'))
H(E B('Must-connect nets VSS of circuit INV2 are not connected') C(INVCHAIN) X('must-connect') Q('(0,0;0,9.2;3,9.2;3,0)'))
K(PMOS MOS3)
K(NMOS MOS3)
D(D$PMOS PMOS
T(S
R(l2 (-900 -475) (775 950))
)
T(G
R(l3 (-125 -475) (250 950))
)
T(D
R(l2 (125 -475) (775 950))
)
)
D(D$NMOS NMOS
T(S
R(l5 (-900 -475) (775 950))
)
T(G
R(l3 (-125 -475) (250 950))
)
T(D
R(l5 (125 -475) (775 950))
)
)
X(INV
R((-1500 -800) (3000 4600))
N(1
R(l6 (290 -310) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -690) (360 760))
R(l9 (-305 -705) (250 250))
R(l9 (-250 150) (250 250))
R(l10 (-2025 -775) (3000 900))
R(l5 (-1375 -925) (775 950))
)
N(2
R(l6 (290 2490) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -690) (360 760))
R(l9 (-305 -705) (250 250))
R(l9 (-250 150) (250 250))
R(l10 (-2025 -775) (3000 900))
R(l2 (-1375 -925) (775 950))
)
N(3
R(l3 (-125 -250) (250 2500))
R(l3 (-250 -3050) (250 1600))
R(l3 (-250 1200) (250 1600))
)
N(4
R(l6 (-510 -310) (220 220))
R(l6 (-220 180) (220 220))
R(l6 (-220 2180) (220 220))
R(l6 (-220 180) (220 220))
R(l8 (-290 -3530) (360 2840))
R(l8 (-360 -2800) (360 760))
R(l8 (-360 2040) (360 760))
R(l2 (-680 -855) (775 950))
R(l5 (-775 -3750) (775 950))
)
P(1)
P(2)
P(3)
P(4)
D(1 D$PMOS
Y(0 2800)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 4)
T(G 3)
T(D 2)
)
D(2 D$NMOS
Y(0 0)
E(L 0.25)
E(W 0.95)
E(AS 0.73625)
E(AD 0.73625)
E(PS 3.45)
E(PD 3.45)
T(S 4)
T(G 3)
T(D 1)
)
)
X(INV2
R((0 0) (3000 9200))
N(1 I(VDD)
R(l10 (0 3150) (3000 2900))
R(l13 (-1890 -1450) (0 0))
)
N(2 I(A1)
R(l11 (1480 7110) (0 0))
)
N(3 I(A2)
R(l11 (1520 1950) (0 0))
)
N(4 I(Q1)
R(l12 (1920 7070) (0 0))
)
N(5 I(Q2)
R(l12 (1940 1950) (0 0))
)
N(6 I(VSS)
R(l13 (2680 8390) (0 0))
R(l13 (-30 -7640) (0 0))
)
P(1 I(VDD))
P(2 I(A1))
P(3 I(A2))
P(4 I(Q1))
P(5 I(Q2))
P(6 I(VSS))
X(1 INV M O(180) Y(1500 800)
P(0 6)
P(1 1)
P(2 3)
P(3 5)
)
X(2 INV O(180) Y(1500 8400)
P(0 6)
P(1 1)
P(2 2)
P(3 4)
)
)
X(INVCHAIN
R((-915 -15) (10415 9215))
N(1
R(l3 (7340 1650) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(2
R(l3 (1625 1835) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(3 I(IN)
R(l3 (-90 6850) (1590 650))
R(l11 (-700 -350) (0 0))
)
N(4 I(IN2)
R(l3 (5665 6790) (1590 650))
R(l11 (-700 -350) (0 0))
)
N(5 I('VSS,VSS2,VSS2B')
R(l10 (-915 5290) (250 2960))
R(l10 (-250 0) (915 250))
R(l10 (-915 -7825) (915 250))
R(l10 (-915 0) (250 3145))
R(l13 (155 4305) (0 0))
R(l13 (8990 -255) (0 0))
R(l13 (25 -7115) (0 0))
)
N(6 I(OUT)
R(l12 (1890 2105) (0 0))
)
N(7 I(OUT2)
R(l12 (7730 2155) (0 0))
)
N(8 I(VDD)
R(l13 (8035 4540) (0 0))
R(l13 (-5735 60) (0 0))
)
P(3 I(IN))
P(4 I(IN2))
P(5 I('VSS,VSS2,VSS2B'))
P(6 I(OUT))
P(7 I(OUT2))
P(8 I(VDD))
X(1 INV2 Y(5780 -15)
P(0 8)
P(1 4)
P(2 1)
P(3 1)
P(4 7)
P(5 5)
)
X(2 INV2 Y(0 0)
P(0 8)
P(1 3)
P(2 2)
P(3 2)
P(4 6)
P(5 5)
)
)
X(TOP
R((-305 350) (15415 9225))
N(1
R(l3 (12950 2130) (2160 250))
R(l3 (-250 0) (250 4990))
R(l3 (-1605 0) (1605 250))
R(l7 (-1545 -250) (240 250))
R(l8 (-560 -375) (690 510))
)
N(2
R(l3 (12100 7300) (640 530))
R(l7 (-540 -415) (270 250))
R(l8 (-1695 -250) (1695 250))
R(l8 (-4075 -5650) (2630 250))
R(l8 (-250 0) (250 5150))
)
N(3
R(l7 (6465 7325) (220 240))
R(l8 (-4100 -5365) (3125 250))
R(l8 (-250 0) (250 4860))
R(l8 (-250 0) (1225 250))
)
N(4 I(VSSTOP)
R(l10 (3610 8300) (2815 440))
R(l10 (-710 -250) (0 0))
R(l10 (3675 -165) (1975 565))
R(l10 (-1975 -8190) (1975 575))
R(l10 (-1005 -255) (0 0))
)
N(5 I(A)
R(l11 (975 7530) (0 0))
)
N(6 I(Q)
R(l12 (13260 2010) (0 0))
)
N(7 I(VDD)
R(l10 (2595 4805) (0 0))
R(l10 (4295 -30) (0 0))
R(l10 (4975 -50) (0 0))
)
P(4 I(VSSTOP))
P(5 I(A))
P(6 I(Q))
P(7 I(VDD))
X(1 INV2 Y(11365 375)
P(0 7)
P(1 2)
P(2 1)
P(3 1)
P(4 6)
P(5 4)
)
X(2 INVCHAIN Y(610 365)
P(0 5)
P(1 3)
P(2 4)
P(3 3)
P(4 2)
P(5 7)
)
)
)
H(
K(PMOS MOS3)
K(NMOS MOS3)
X(INV
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A))
N(4 I(Q))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A))
P(4 I(Q))
D(1 PMOS
I($1)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 1)
T(G 3)
T(D 4)
)
D(2 NMOS
I($3)
E(L 0.25)
E(W 0.95)
E(AS 0)
E(AD 0)
E(PS 0)
E(PD 0)
T(S 2)
T(G 3)
T(D 4)
)
)
X(INV2
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A1))
N(4 I(Q1))
N(5 I(A2))
N(6 I(Q2))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A1))
P(4 I(Q1))
P(5 I(A2))
P(6 I(Q2))
X(1 INV I($1)
P(0 1)
P(1 2)
P(2 3)
P(3 4)
)
X(2 INV I($2)
P(0 1)
P(1 2)
P(2 5)
P(3 6)
)
)
X(INVCHAIN
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A1))
N(4 I(Q1))
N(5 I(A2))
N(6 I(Q2))
N(7 I('1'))
N(8 I('2'))
P(1 I(VDD))
P(2 I(VSS))
P(3 I(A1))
P(4 I(Q1))
P(5 I(A2))
P(6 I(Q2))
X(1 INV2 I($2)
P(0 1)
P(1 2)
P(2 3)
P(3 7)
P(4 7)
P(5 4)
)
X(2 INV2 I($3)
P(0 1)
P(1 2)
P(2 5)
P(3 8)
P(4 8)
P(5 6)
)
)
X(TOP
N(1 I(VDD))
N(2 I(VSS))
N(3 I(A))
N(4 I('1'))
N(5 I('3'))
N(6 I('2'))
N(7 I(Q))
X(1 INVCHAIN I($1)
P(0 1)
P(1 2)
P(2 3)
P(3 4)
P(4 4)
P(5 5)
)
X(2 INV2 I($2)
P(0 1)
P(1 2)
P(2 5)
P(3 6)
P(4 6)
P(5 7)
)
)
)
Z(
X(INV INV 1
Z(
N(3 3 1)
N(4 4 1)
N(2 1 1)
N(1 2 1)
P(2 2 1)
P(3 3 1)
P(1 0 1)
P(0 1 1)
D(2 2 1)
D(1 1 1)
)
)
X(INV2 INV2 1
Z(
N(2 3 1)
N(3 5 1)
N(4 4 1)
N(5 6 1)
N(1 1 1)
N(6 2 1)
P(1 2 1)
P(2 4 1)
P(3 3 1)
P(4 5 1)
P(0 0 1)
P(5 1 1)
X(2 1 1)
X(1 2 1)
)
)
X(INVCHAIN INVCHAIN 1
L(
M(W B('Matching nets OUT vs. Q1 from an ambiguous group of nets'))
M(W B('Matching nets OUT2 vs. Q2 from an ambiguous group of nets'))
M(I B('Matching nets $2 vs. 1 following an ambiguous match'))
M(I B('Matching nets IN vs. A1 following an ambiguous match'))
M(I B('Matching nets $1 vs. 2 following an ambiguous match'))
M(I B('Matching nets IN2 vs. A2 following an ambiguous match'))
)
Z(
N(2 7 1)
N(1 8 1)
N(3 3 1)
N(4 5 1)
N(6 4 W)
N(7 6 W)
N(8 1 1)
N(5 2 1)
P(0 2 1)
P(1 4 1)
P(3 3 1)
P(4 5 1)
P(5 0 1)
P(2 1 1)
X(2 1 1)
X(1 2 1)
)
)
X(TOP TOP 1
Z(
N(3 4 1)
N(1 6 1)
N(2 5 1)
N(5 3 1)
N(6 7 1)
N(7 1 1)
N(4 2 1)
P(1 () 1)
P(2 () 1)
P(3 () 1)
P(0 () 1)
X(1 2 1)
X(2 1 1)
)
)
)
testdata/lvs/must_connect2.sch
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+24
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@@ -0,0 +1,24 @@
.SUBCKT TOP
X$1 VDD VSS A 1 1 3 INVCHAIN
X$2 VDD VSS 3 2 2 Q INV2
.ENDS TOP
* cell INVCHAIN
.SUBCKT INVCHAIN VDD VSS A1 Q1 A2 Q2
X$2 VDD VSS A1 1 1 Q1 INV2
X$3 VDD VSS A2 2 2 Q2 INV2
.ENDS INVCHAIN
* cell INV2
.SUBCKT INV2 VDD VSS A1 Q1 A2 Q2
X$1 VDD VSS A1 Q1 INV
X$2 VDD VSS A2 Q2 INV
.ENDS INV2
* cell INV
.SUBCKT INV VDD VSS A Q
M$1 VDD A Q VDD PMOS L=0.25U W=0.95U
M$3 VSS A Q VSS NMOS L=0.25U W=0.95U
.ENDS INV
testdata/lvs/ringo_simple_dmos.lvsdb.1
Vendored
+3
View File
@@ -832,6 +832,9 @@ reference(
# Cross reference
xref(
log(
entry(error description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1'))
)
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
testdata/lvs/ringo_simple_dmos.lvsdb.2
Vendored
+3
View File
@@ -832,6 +832,9 @@ reference(
# Cross reference
xref(
log(
entry(error description('Circuits RINGO and RINGO could not be compared because the following subcircuits failed to compare:\n A: ND2X1\n B: ND2X1'))
)
circuit(INVX1 INVX1 match
xref(
net(4 4 match)
testdata/lvs/ringo_simple_implicit_connections.lvsdb.1
Vendored
+35 -32
View File
@@ -38,6 +38,9 @@ layout(
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Log entries
message(warning description('Must-connect nets VDD must be connected further up in the hierarchy - this is an error at chip top level') cell(RINGO) cat('must-connect'))
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
@@ -404,36 +407,36 @@ layout(
)
net(12 name(VDD)
rect(l3 (22600 4500) (1400 3500))
rect(l3 (-23500 -3500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (25800 -3500) (1400 3500))
rect(l3 (2400 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-5090 -1240) (180 180))
rect(l3 (-27800 -3500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l8 (22610 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (3620 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (25720 370) (180 180))
rect(l8 (-26080 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-4890 1010) (0 0))
rect(l11 (21010 1010) (0 0))
rect(l11 (2800 -50) (0 0))
rect(l11 (-22150 -100) (0 0))
rect(l11 (19750 -450) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-22750 -400) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (25900 -800) (1200 800))
rect(l11 (3150 -400) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (550 -400) (600 800))
rect(l9 (-5250 -1500) (500 1500))
rect(l9 (-22600 -1500) (500 1500))
rect(l9 (25400 -1500) (500 1500))
rect(l11 (-27700 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l9 (22450 -1500) (500 1500))
rect(l9 (3300 -1500) (500 1500))
rect(l9 (-26400 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (25990 3840) (320 320))
@@ -448,32 +451,32 @@ layout(
rect(l13 (-150 -200) (400 400))
)
net(15 name(VSS)
rect(l8 (27010 1610) (180 180))
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-3980 370) (180 180))
rect(l8 (21920 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (3620 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (24710 -290) (0 0))
rect(l11 (-3850 0) (0 0))
rect(l11 (-19200 -100) (0 0))
rect(l11 (24000 -400) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (550 -400) (600 800))
rect(l11 (-5150 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (-22300 -350) (300 1400))
rect(l11 (-24240 -390) (0 0))
rect(l11 (19200 100) (0 0))
rect(l11 (3850 0) (0 0))
rect(l11 (-24950 -500) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l10 (26250 -800) (500 1500))
rect(l10 (-4300 -1500) (500 1500))
rect(l10 (-22600 -1500) (500 1500))
rect(l11 (22550 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (3600 -350) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (550 -400) (600 800))
rect(l10 (-27350 -800) (500 1500))
rect(l10 (21600 -1500) (500 1500))
rect(l10 (3300 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
testdata/lvs/ringo_simple_implicit_connections.lvsdb.2
Vendored
+35 -32
View File
@@ -38,6 +38,9 @@ layout(
global(l7 SUBSTRATE)
global(l10 SUBSTRATE)
# Log entries
message(warning description('Must-connect nets VDD must be connected further up in the hierarchy - this is an error at chip top level') cell(RINGO) cat('must-connect'))
# Device class section
class(PMOS MOS4)
class(NMOS MOS4)
@@ -404,36 +407,36 @@ layout(
)
net(12 name(VDD)
rect(l3 (22600 4500) (1400 3500))
rect(l3 (-23500 -3500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l3 (25800 -3500) (1400 3500))
rect(l3 (2400 -3500) (1400 3500))
rect(l3 (-100 -3500) (600 3500))
rect(l8 (-5090 -1240) (180 180))
rect(l3 (-27800 -3500) (1400 3500))
rect(l3 (-1900 -3500) (600 3500))
rect(l8 (22610 -1240) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (3620 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (25720 370) (180 180))
rect(l8 (-26080 370) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l11 (-4890 1010) (0 0))
rect(l11 (21010 1010) (0 0))
rect(l11 (2800 -50) (0 0))
rect(l11 (-22150 -100) (0 0))
rect(l11 (19750 -450) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-22750 -400) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l11 (25900 -800) (1200 800))
rect(l11 (3150 -400) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (550 -400) (600 800))
rect(l9 (-5250 -1500) (500 1500))
rect(l9 (-22600 -1500) (500 1500))
rect(l9 (25400 -1500) (500 1500))
rect(l11 (-27700 -800) (1200 800))
rect(l11 (-750 -1450) (300 1400))
rect(l11 (-100 -350) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l9 (22450 -1500) (500 1500))
rect(l9 (3300 -1500) (500 1500))
rect(l9 (-26400 -1500) (500 1500))
)
net(13 name(OUT)
rect(l11 (25990 3840) (320 320))
@@ -448,32 +451,32 @@ layout(
rect(l13 (-150 -200) (400 400))
)
net(15 name(VSS)
rect(l8 (27010 1610) (180 180))
rect(l8 (1110 1610) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-3980 370) (180 180))
rect(l8 (21920 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l8 (-22280 370) (180 180))
rect(l8 (3620 370) (180 180))
rect(l8 (-180 -1280) (180 180))
rect(l8 (-180 370) (180 180))
rect(l11 (24710 -290) (0 0))
rect(l11 (-3850 0) (0 0))
rect(l11 (-19200 -100) (0 0))
rect(l11 (24000 -400) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (550 -400) (600 800))
rect(l11 (-5150 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (-22300 -350) (300 1400))
rect(l11 (-24240 -390) (0 0))
rect(l11 (19200 100) (0 0))
rect(l11 (3850 0) (0 0))
rect(l11 (-24950 -500) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (-1250 -400) (600 800))
rect(l10 (26250 -800) (500 1500))
rect(l10 (-4300 -1500) (500 1500))
rect(l10 (-22600 -1500) (500 1500))
rect(l11 (22550 -750) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (3600 -350) (300 1400))
rect(l11 (-750 -1450) (1200 800))
rect(l11 (-550 -400) (0 0))
rect(l11 (550 -400) (600 800))
rect(l10 (-27350 -800) (500 1500))
rect(l10 (21600 -1500) (500 1500))
rect(l10 (3300 -1500) (500 1500))
)
# Outgoing pins and their connections to nets
testdata/lvs/test_22a.lvsdb.1
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22a.lvsdb.2
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22b.lvsdb.1
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22b.lvsdb.2
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l1 vss)
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22c.lvsdb.1
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22c.lvsdb.2
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22c.lvsdb.3
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22d.lvsdb.1
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22d.lvsdb.2
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/lvs/test_22d.lvsdb.3
Vendored
+3
View File
@@ -70,6 +70,9 @@ layout(
global(l6 vss)
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at chip top level') cell(SP6TArray_2X4) cat('must-connect'))
# Device class section
class(active_res RES)
class(poly_res RES)
testdata/ruby/dbLayoutToNetlist.rb
Vendored
+14
View File
@@ -1011,6 +1011,20 @@ END
end
def test_21_LogAPI
l2n = RBA::LayoutToNetlist::new
l2n.read(File.join($ut_testsrc, "testdata", "algo", "l2n_reader_au_6.l2n"))
le = l2n.each_log_entry.collect { |s| s.to_s }
assert_equal(le.size, 4)
assert_equal(le[0].to_s, "info")
assert_equal(le[1].to_s, "[cat description] In cell cell_name: info, shape: (1,1;2,2;3,1)")
assert_equal(le[2].to_s, "warning")
assert_equal(le[3].to_s, "error")
end
end
load("test_epilogue.rb")
testdata/ruby/dbLogTest.rb
Vendored
+59
View File
@@ -0,0 +1,59 @@
# encoding: UTF-8
# KLayout Layout Viewer
# Copyright (C) 2006-2023 Matthias Koefferlein
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program; if not, write to the Free Software
# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
if !$:.member?(File::dirname($0))
$:.push(File::dirname($0))
end
load("test_prologue.rb")
class DBLog_TestClass < TestBase
def test_1_Log
assert_equal(RBA::LogEntryData::NoSeverity.to_s, "NoSeverity")
assert_equal(RBA::LogEntryData::Info.to_s, "Info")
assert_equal(RBA::LogEntryData::Error.to_s, "Error")
assert_equal(RBA::LogEntryData::Warning.to_s, "Warning")
le = RBA::LogEntryData::new
le.message = "message"
assert_equal(le.message, "message")
le.geometry = RBA::DPolygon::new(RBA::DBox::new(1, 2, 3, 4))
assert_equal(le.geometry.to_s, "(1,2;1,4;3,4;3,2)")
le.category_name = "42"
assert_equal(le.category_name, "42")
le.category_description = "the answer"
assert_equal(le.category_description, "the answer")
le.cell_name = "TOP"
assert_equal(le.cell_name, "TOP")
assert_equal(le.to_s, "[the answer] In cell TOP: message, shape: (1,2;1,4;3,4;3,2)")
end
end
load("test_epilogue.rb")
testdata/ruby/dbNetlist.rb
Vendored
+5 -5
View File
@@ -1120,11 +1120,11 @@ END
c.join_nets(c.net_by_name("IN"), c.net_by_name("OUT"))
assert_equal(nl.to_s, <<"END")
circuit INV2 (IN=IN,$2=$2,OUT=IN,$4=$4,$5=$5);
subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);
subcircuit PTRANS SC3 ($1=$5,$2=IN,$3=$2);
subcircuit NTRANS SC4 ($1=$4,$2=IN,$3=$2);
circuit INV2 ('IN,OUT'='IN,OUT',$2=$2,$3=$4,$4=$5);
subcircuit PTRANS SC1 ($1=$5,$2=$2,$3='IN,OUT');
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3='IN,OUT');
subcircuit PTRANS SC3 ($1=$5,$2='IN,OUT',$3=$2);
subcircuit NTRANS SC4 ($1=$4,$2='IN,OUT',$3=$2);
end;
circuit PTRANS ($1=$1,$2=$2,$3=$3);
device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);
testdata/ruby/dbNetlistCompare.rb
Vendored
+6
View File
@@ -181,6 +181,12 @@ class NetlistCompare_TestClass < TestBase
def test_1
# severity enums
assert_equal(NetlistCompareTestLogger::Info.to_s, "Info")
assert_equal(NetlistCompareTestLogger::Error.to_s, "Error")
assert_equal(NetlistCompareTestLogger::Warning.to_s, "Warning")
assert_equal(NetlistCompareTestLogger::NoSeverity.to_s, "NoSeverity")
nl1 = RBA::Netlist::new
nl2 = RBA::Netlist::new
dc = RBA::DeviceClass::new
testdata/ruby/dbNetlistDeviceExtractors.rb
Vendored
+1 -1
View File
@@ -27,7 +27,7 @@ class DBNetlistExtractorTests_TestClass < TestBase
def test_1_Error
err = RBA::NetlistDeviceExtractorError::new
err = RBA::LogEntryData::new
err.message = "MSG"
err.cell_name = "Cell"