mirror of https://github.com/KLayout/klayout.git
Added 'top_level' feature to tell LVS to perform in top level mode
This commit is contained in:
Matthias Koefferlein
parent
583232c7f4
commit
72278b90ec
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@ -45,7 +45,7 @@ namespace db
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// Note: the iterator provides the hierarchical selection (enabling/disabling cells etc.)
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LayoutToNetlist::LayoutToNetlist (const db::RecursiveShapeIterator &iter)
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: m_iter (iter), m_layout_index (0), m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0), m_include_floating_subcircuits (false)
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: m_iter (iter), m_layout_index (0), m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0), m_include_floating_subcircuits (false), m_top_level_mode (false)
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{
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// check the iterator
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if (iter.has_complex_region () || iter.region () != db::Box::world ()) {
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@ -65,7 +65,7 @@ LayoutToNetlist::LayoutToNetlist (const db::RecursiveShapeIterator &iter)
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}
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LayoutToNetlist::LayoutToNetlist (db::DeepShapeStore *dss, unsigned int layout_index)
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: mp_dss (dss), m_layout_index (layout_index), m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0), m_include_floating_subcircuits (false)
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: mp_dss (dss), m_layout_index (layout_index), m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0), m_include_floating_subcircuits (false), m_top_level_mode (false)
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{
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if (dss->is_valid_layout_index (m_layout_index)) {
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m_iter = db::RecursiveShapeIterator (dss->layout (m_layout_index), dss->initial_cell (m_layout_index), std::set<unsigned int> ());
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@ -73,7 +73,7 @@ LayoutToNetlist::LayoutToNetlist (db::DeepShapeStore *dss, unsigned int layout_i
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}
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LayoutToNetlist::LayoutToNetlist (const std::string &topcell_name, double dbu)
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: m_iter (), m_netlist_extracted (false), m_is_flat (true), m_device_scaling (1.0), m_include_floating_subcircuits (false)
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: m_iter (), m_netlist_extracted (false), m_is_flat (true), m_device_scaling (1.0), m_include_floating_subcircuits (false), m_top_level_mode (false)
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{
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mp_internal_dss.reset (new db::DeepShapeStore (topcell_name, dbu));
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mp_dss.reset (mp_internal_dss.get ());
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@ -84,7 +84,7 @@ LayoutToNetlist::LayoutToNetlist (const std::string &topcell_name, double dbu)
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LayoutToNetlist::LayoutToNetlist ()
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: m_iter (), mp_internal_dss (new db::DeepShapeStore ()), mp_dss (mp_internal_dss.get ()), m_layout_index (0),
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m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0), m_include_floating_subcircuits (false)
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m_netlist_extracted (false), m_is_flat (false), m_device_scaling (1.0), m_include_floating_subcircuits (false), m_top_level_mode (false)
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{
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init ();
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}
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@ -488,12 +488,12 @@ void LayoutToNetlist::check_must_connect (const db::Circuit &c, const db::Net &a
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}
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} else {
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if (a.expanded_name () == b.expanded_name ()) {
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db::LogEntryData warn (db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s must be connected further up in the hierarchy - this is an error at chip top level")), a.expanded_name ()));
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db::LogEntryData warn (m_top_level_mode ? db::Error : db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s must be connected further up in the hierarchy - this is an error at chip top level")), a.expanded_name ()));
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warn.set_cell_name (c.name ());
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warn.set_category_name ("must-connect");
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log_entry (warn);
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} else {
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db::LogEntryData warn (db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s and %s must be connected further up in the hierarchy - this is an error at chip top level")), a.expanded_name (), b.expanded_name ()));
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db::LogEntryData warn (m_top_level_mode ? db::Error : db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s and %s must be connected further up in the hierarchy - this is an error at chip top level")), a.expanded_name (), b.expanded_name ()));
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warn.set_cell_name (c.name ());
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warn.set_category_name ("must-connect");
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log_entry (warn);
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@ -192,6 +192,27 @@ public:
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m_filename = filename;
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}
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/**
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* @brief Gets the top level mode flag
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*/
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bool top_level_mode () const
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{
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return m_top_level_mode;
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}
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/**
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* @brief Sets top level mode
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*
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* In top level mode, must-connect warnings are turned into
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* errors for example.
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*
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* By default, top-level mode is off.
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*/
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void set_top_level_mode (bool f)
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{
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m_top_level_mode = f;
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}
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/**
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* @brief Gets the log entries
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*/
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@ -999,6 +1020,7 @@ private:
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db::DeepLayer m_dummy_layer;
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std::string m_generator;
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bool m_include_floating_subcircuits;
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bool m_top_level_mode;
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std::list<tl::GlobPattern> m_joined_net_names;
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std::list<std::pair<tl::GlobPattern, tl::GlobPattern> > m_joined_net_names_per_cell;
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std::list<std::set<std::string> > m_joined_nets;
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@ -464,6 +464,20 @@ Class<db::LayoutToNetlist> decl_dbLayoutToNetlist ("db", "LayoutToNetlist",
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"\n"
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"This attribute has been introduced in version 0.27.\n"
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) +
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gsi::method ("top_level_mode=", &db::LayoutToNetlist::set_top_level_mode, gsi::arg ("flag"),
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"@brief Sets a flag indicating whether top level mode is enabled.\n"
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"\n"
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"In top level mode, must-connect warnings are turned into errors for example.\n"
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"To enable top level mode, set this attribute to true. By default, top-level mode is turned off.\n"
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"\n"
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"This attribute has been introduced in version 0.28.13."
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) +
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gsi::method ("top_level_mode", &db::LayoutToNetlist::top_level_mode,
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"@brief Gets a flag indicating whether top level mode is enabled.\n"
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"See \\top_level_mode= for details.\n"
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"\n"
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"This attribute has been introduced in version 0.28.13.\n"
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) +
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gsi::method ("clear_join_net_names", &db::LayoutToNetlist::clear_join_net_names,
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"@brief Clears all implicit net joining expressions.\n"
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"See \\extract_netlist for more details about this feature.\n"
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@ -137,7 +137,14 @@ connect(metal2, metal2_labels)</pre>
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</p>
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<p>
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This feature is also called "must connect" nets in other systems.
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You can declare the layout as being a top level one. This turns the
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warning about missing physical connections into an error:
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</p>
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<pre>top_level(true)</pre>
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<p>
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The "connect_implicit" feature is also called "must connect" nets in other systems.
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</p>
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<p>
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@ -222,11 +229,11 @@ connect(metal2, metal2_labels)</pre>
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To align layout and schematic, bulk and VSS pins can be connected
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explicitly. Same for n-well and VDD.
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This scheme is similar to the "connect_implicit" scheme explained
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above, but acts on differently named nets.
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above, but can connect differently named nets.
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</p>
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<p>
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To establish an explicit connection, make sure that n-well and
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To establish an explicit connection in the above example, make sure that n-well and
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bulk have proper names. For the n-well this can be done by creating
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labels on the n-well islands giving them a proper name - e.g. "NWELL".
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The bulk isn't a real layout layer with polygons on it. Using "connect_global"
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@ -257,8 +264,7 @@ connect_explicit("INV", [ "BULK", "VSS" ])
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<p>
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Like implicit connections, explicit connections are checked for being made
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on the next level of hierarchy, either physically or by another explicit or
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implicit connection.
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This feature is also called "must connect" nets in other systems.
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implicit connection.
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</p>
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<p>
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@ -2277,6 +2277,12 @@ CODE
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# @synopsis device_scaling(factor)
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# See \Netter#device_scaling for a description of that function.
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# %DRC%
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# @name top_level
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# @brief Specifies that the circuit is a chip top level circuit
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# @synopsis top_level(flag)
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# See \Netter#top_level for a description of that function.
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# %DRC%
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# @name ignore_extraction_errors
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# @brief Specifies whether to ignore extraction errors
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@ -2305,6 +2311,7 @@ CODE
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connect_implicit
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connect_explicit
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device_scaling
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top_level
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ignore_extraction_errors
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extract_devices
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l2n_data
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@ -70,6 +70,7 @@ module DRC
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@lnum = 0
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@device_scaling = 1.0
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@ignore_extraction_errors = false
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@top_level = false
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end
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# %DRC%
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@ -236,6 +237,24 @@ module DRC
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end
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end
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# %DRC%
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# @name top_level
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# @brief Specifies top level mode
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# @synopsis top_level(value)
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# With this value set to false (the default), it is assumed that the
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# circuit is not used as a top level chip circuit. In that case, for
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# example must-connect nets which are not connected are reported as
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# as warnings. If top level mode is set to true, such disconnected
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# nets are reported as errors as this indicates a missing physical
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# connection.
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def top_level(value)
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@engine._context("top_level") do
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@top_level = value
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@l2n && @l2n.top_level_mode = value
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end
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end
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# %DRC%
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# @name ignore_extraction_errors
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# @brief Specifies whether to ignore extraction errors
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@ -672,6 +691,7 @@ module DRC
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@layers = {}
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_make_data
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@l2n.device_scaling = @device_scaling
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@l2n.top_level_mode = @top_level
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end
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end
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@ -279,9 +279,11 @@ TEST(29_DeviceCombineAndTolerances)
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TEST(30_MustConnect1)
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{
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run_test (_this, "must_connect1", "must_connect1.gds");
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run_test (_this, "must_connect1_tl", "must_connect1.gds");
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}
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TEST(31_MustConnect2)
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{
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run_test (_this, "must_connect2", "must_connect2.gds");
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}
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@ -0,0 +1,23 @@
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* Extracted by KLayout
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.SUBCKT TOP VSSTOP A Q
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X$1 \$8 \$2 \$1 \$1 Q VSSTOP INV2
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X$2 A \$3 VSSTOP \$3 \$2 \$8 INVCHAIN
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.ENDS TOP
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.SUBCKT INVCHAIN IN IN2 VSS|VSS2|VSS2B OUT OUT2 VDD
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X$1 VDD IN2 \$1 \$1 OUT2 VSS|VSS2|VSS2B INV2
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X$2 VDD IN \$2 \$2 OUT VSS|VSS2|VSS2B INV2
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.ENDS INVCHAIN
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.SUBCKT INV2 VDD A1 A2 Q1 Q2 VSS
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X$1 VSS VDD A2 Q2 INV
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X$2 VSS VDD A1 Q1 INV
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.ENDS INV2
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.SUBCKT INV \$1 \$2 \$3 \$4
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M$1 \$2 \$3 \$4 \$4 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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M$2 \$1 \$3 \$4 \$4 NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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.ENDS INV
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@ -0,0 +1,143 @@
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$lvs_test_source && source($lvs_test_source)
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if $lvs_test_target_lvsdb
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report_lvs($lvs_test_target_lvsdb)
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else
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report_lvs
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end
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writer = write_spice(true, false)
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$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
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# Turns the warning about VSSTOP into an error
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top_level(true)
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ignore_extraction_errors(true)
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# needs this delegate because we use MOS3 which is not available in Spice
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class SpiceReaderDelegate < RBA::NetlistSpiceReaderDelegate
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# says we want to catch these subcircuits as devices
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def wants_subcircuit(name)
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name == "HVNMOS" || name == "HVPMOS"
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end
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# translate the element
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def element(circuit, el, name, model, value, nets, params)
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if el != "M"
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# all other elements are left to the standard implementation
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return super
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end
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if nets.size != 4
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error("Device #{model} needs four nodes")
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end
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# provide a device class
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cls = circuit.netlist.device_class_by_name(model)
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if ! cls
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cls = RBA::DeviceClassMOS3Transistor::new
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cls.name = model
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circuit.netlist.add(cls)
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end
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# create a device
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device = circuit.create_device(cls, name)
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# and configure the device
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[ "S", "G", "D" ].each_with_index do |t,index|
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device.connect_terminal(t, nets[index])
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end
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device.set_parameter("W", params["W"] * 1e6)
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device.set_parameter("L", params["L"] * 1e6)
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device
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end
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end
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reader = RBA::NetlistSpiceReader::new(SpiceReaderDelegate::new)
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schematic(File.basename(source.path, ".*") + ".sch", reader)
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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poly = input(3, 0)
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poly_lbl = input(3, 1)
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diff_cont = input(4, 0)
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poly_cont = input(5, 0)
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metal1 = input(6, 0)
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metal1_lbl = input(6, 1)
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via1 = input(7, 0)
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metal2 = input(8, 0)
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metal2_lbl = input(8, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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psd = nil
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nsd = nil
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos3("PMOS"), { "SD" => psd, "G" => pgate,
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"tS" => psd, "tD" => psd, "tG" => poly })
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# NMOS transistor device extraction
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extract_devices(mos3("NMOS"), { "SD" => nsd, "G" => ngate,
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"tS" => nsd, "tD" => nsd, "tG" => poly })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, diff_cont)
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connect(nsd, diff_cont)
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connect(poly, poly_cont)
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connect(diff_cont, metal1)
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connect(poly_cont, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# attach labels
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connect(poly, poly_lbl)
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connect(metal1, metal1_lbl)
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connect(metal2, metal2_lbl)
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# Global
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connect_global(bulk, "SUBSTRATE")
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# Implicit connection of the INV2
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# VSS nets
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connect_implicit("INV2", "VSS")
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connect_implicit("TOP", "VSS*")
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# Fix 1
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connect_explicit("INVCHAIN", ["VSS2", "VSS2B", "VSS"])
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connect_implicit("INVCHAIN", "VDD")
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# Compare section
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netlist.simplify
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align
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compare
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@ -0,0 +1,484 @@
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#%lvsdb-klayout
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J(
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W(TOP)
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U(0.001)
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L(l3 '3/0')
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L(l11 '3/1')
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L(l6 '4/0')
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L(l7 '5/0')
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L(l8 '6/0')
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L(l12 '6/1')
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L(l9 '7/0')
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L(l10 '8/0')
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L(l13 '8/1')
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L(l14)
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L(l2)
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L(l5)
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C(l3 l3 l11 l7)
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C(l11 l3 l11)
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C(l6 l6 l8 l2 l5)
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C(l7 l3 l7 l8)
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C(l8 l6 l7 l8 l12 l9)
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C(l12 l8 l12)
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C(l9 l8 l9 l10)
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C(l10 l9 l10 l13)
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C(l13 l10 l13)
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C(l14 l14)
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C(l2 l6 l2)
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C(l5 l6 l5)
|
||||
G(l14 SUBSTRATE)
|
||||
H(E B('Must-connect nets VSSTOP must be connected further up in the hierarchy - this is an error at chip top level') C(TOP) X('must-connect'))
|
||||
K(PMOS MOS3)
|
||||
K(NMOS MOS3)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l5 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l5 (125 -475) (775 950))
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3000 4600))
|
||||
N(1
|
||||
R(l6 (290 -310) (220 220))
|
||||
R(l6 (-220 180) (220 220))
|
||||
R(l8 (-290 -690) (360 760))
|
||||
R(l9 (-305 -705) (250 250))
|
||||
R(l9 (-250 150) (250 250))
|
||||
R(l10 (-2025 -775) (3000 900))
|
||||
R(l5 (-1375 -925) (775 950))
|
||||
)
|
||||
N(2
|
||||
R(l6 (290 2490) (220 220))
|
||||
R(l6 (-220 180) (220 220))
|
||||
R(l8 (-290 -690) (360 760))
|
||||
R(l9 (-305 -705) (250 250))
|
||||
R(l9 (-250 150) (250 250))
|
||||
R(l10 (-2025 -775) (3000 900))
|
||||
R(l2 (-1375 -925) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l3 (-125 -250) (250 2500))
|
||||
R(l3 (-250 -3050) (250 1600))
|
||||
R(l3 (-250 1200) (250 1600))
|
||||
)
|
||||
N(4
|
||||
R(l6 (-510 -310) (220 220))
|
||||
R(l6 (-220 180) (220 220))
|
||||
R(l6 (-220 2180) (220 220))
|
||||
R(l6 (-220 180) (220 220))
|
||||
R(l8 (-290 -3530) (360 2840))
|
||||
R(l8 (-360 -2800) (360 760))
|
||||
R(l8 (-360 2040) (360 760))
|
||||
R(l2 (-680 -855) (775 950))
|
||||
R(l5 (-775 -3750) (775 950))
|
||||
)
|
||||
P(1)
|
||||
P(2)
|
||||
P(3)
|
||||
P(4)
|
||||
D(1 D$PMOS
|
||||
Y(0 2800)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 4)
|
||||
T(G 3)
|
||||
T(D 2)
|
||||
)
|
||||
D(2 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 4)
|
||||
T(G 3)
|
||||
T(D 1)
|
||||
)
|
||||
)
|
||||
X(INV2
|
||||
R((0 0) (3000 9200))
|
||||
N(1 I(VDD)
|
||||
R(l10 (0 3150) (3000 2900))
|
||||
R(l13 (-1890 -1450) (0 0))
|
||||
)
|
||||
N(2 I(A1)
|
||||
R(l11 (1480 7110) (0 0))
|
||||
)
|
||||
N(3 I(A2)
|
||||
R(l11 (1520 1950) (0 0))
|
||||
)
|
||||
N(4 I(Q1)
|
||||
R(l12 (1920 7070) (0 0))
|
||||
)
|
||||
N(5 I(Q2)
|
||||
R(l12 (1940 1950) (0 0))
|
||||
)
|
||||
N(6 I(VSS)
|
||||
R(l13 (2680 8390) (0 0))
|
||||
R(l13 (-30 -7640) (0 0))
|
||||
)
|
||||
P(1 I(VDD))
|
||||
P(2 I(A1))
|
||||
P(3 I(A2))
|
||||
P(4 I(Q1))
|
||||
P(5 I(Q2))
|
||||
P(6 I(VSS))
|
||||
X(1 INV M O(180) Y(1500 800)
|
||||
P(0 6)
|
||||
P(1 1)
|
||||
P(2 3)
|
||||
P(3 5)
|
||||
)
|
||||
X(2 INV O(180) Y(1500 8400)
|
||||
P(0 6)
|
||||
P(1 1)
|
||||
P(2 2)
|
||||
P(3 4)
|
||||
)
|
||||
)
|
||||
X(INVCHAIN
|
||||
R((-915 -15) (10415 9215))
|
||||
N(1
|
||||
R(l3 (7340 1650) (2160 250))
|
||||
R(l3 (-250 0) (250 4990))
|
||||
R(l3 (-1605 0) (1605 250))
|
||||
R(l7 (-1545 -250) (240 250))
|
||||
R(l8 (-560 -375) (690 510))
|
||||
)
|
||||
N(2
|
||||
R(l3 (1625 1835) (2160 250))
|
||||
R(l3 (-250 0) (250 4990))
|
||||
R(l3 (-1605 0) (1605 250))
|
||||
R(l7 (-1545 -250) (240 250))
|
||||
R(l8 (-560 -375) (690 510))
|
||||
)
|
||||
N(3 I(IN)
|
||||
R(l3 (-90 6850) (1590 650))
|
||||
R(l11 (-700 -350) (0 0))
|
||||
)
|
||||
N(4 I(IN2)
|
||||
R(l3 (5665 6790) (1590 650))
|
||||
R(l11 (-700 -350) (0 0))
|
||||
)
|
||||
N(5 I('VSS,VSS2,VSS2B')
|
||||
R(l10 (-915 675) (915 250))
|
||||
R(l10 (-915 0) (250 7325))
|
||||
R(l10 (-250 0) (915 250))
|
||||
R(l13 (-510 -125) (0 0))
|
||||
R(l13 (8990 -255) (0 0))
|
||||
R(l13 (25 -7115) (0 0))
|
||||
)
|
||||
N(6 I(OUT)
|
||||
R(l12 (1890 2105) (0 0))
|
||||
)
|
||||
N(7 I(OUT2)
|
||||
R(l12 (7730 2155) (0 0))
|
||||
)
|
||||
N(8 I(VDD)
|
||||
R(l13 (8035 4540) (0 0))
|
||||
R(l13 (-5735 60) (0 0))
|
||||
)
|
||||
P(3 I(IN))
|
||||
P(4 I(IN2))
|
||||
P(5 I('VSS,VSS2,VSS2B'))
|
||||
P(6 I(OUT))
|
||||
P(7 I(OUT2))
|
||||
P(8 I(VDD))
|
||||
X(1 INV2 Y(5780 -15)
|
||||
P(0 8)
|
||||
P(1 4)
|
||||
P(2 1)
|
||||
P(3 1)
|
||||
P(4 7)
|
||||
P(5 5)
|
||||
)
|
||||
X(2 INV2 Y(0 0)
|
||||
P(0 8)
|
||||
P(1 3)
|
||||
P(2 2)
|
||||
P(3 2)
|
||||
P(4 6)
|
||||
P(5 5)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((-305 350) (15415 9225))
|
||||
N(1
|
||||
R(l3 (12950 2130) (2160 250))
|
||||
R(l3 (-250 0) (250 4990))
|
||||
R(l3 (-1605 0) (1605 250))
|
||||
R(l7 (-1545 -250) (240 250))
|
||||
R(l8 (-560 -375) (690 510))
|
||||
)
|
||||
N(2
|
||||
R(l3 (12100 7300) (640 530))
|
||||
R(l7 (-540 -415) (270 250))
|
||||
R(l8 (-1695 -250) (1695 250))
|
||||
R(l8 (-4075 -5650) (2630 250))
|
||||
R(l8 (-250 0) (250 5150))
|
||||
)
|
||||
N(3
|
||||
R(l7 (6465 7325) (220 240))
|
||||
R(l8 (-4100 -5365) (3125 250))
|
||||
R(l8 (-250 0) (250 4860))
|
||||
R(l8 (-250 0) (1225 250))
|
||||
)
|
||||
N(4 I(VSSTOP)
|
||||
R(l10 (3610 8300) (2815 440))
|
||||
R(l10 (-710 -250) (0 0))
|
||||
R(l10 (3675 -165) (1975 565))
|
||||
R(l10 (-1975 -8190) (1975 575))
|
||||
R(l10 (-1005 -255) (0 0))
|
||||
)
|
||||
N(5 I(A)
|
||||
R(l11 (975 7530) (0 0))
|
||||
)
|
||||
N(6 I(Q)
|
||||
R(l12 (13260 2010) (0 0))
|
||||
)
|
||||
N(7
|
||||
R(l10 (3450 4840) (3055 250))
|
||||
R(l10 (2885 -250) (1975 250))
|
||||
)
|
||||
P(4 I(VSSTOP))
|
||||
P(5 I(A))
|
||||
P(6 I(Q))
|
||||
X(1 INV2 Y(11365 375)
|
||||
P(0 7)
|
||||
P(1 2)
|
||||
P(2 1)
|
||||
P(3 1)
|
||||
P(4 6)
|
||||
P(5 4)
|
||||
)
|
||||
X(2 INVCHAIN Y(610 365)
|
||||
P(0 5)
|
||||
P(1 3)
|
||||
P(2 4)
|
||||
P(3 3)
|
||||
P(4 2)
|
||||
P(5 7)
|
||||
)
|
||||
)
|
||||
)
|
||||
H(
|
||||
K(PMOS MOS3)
|
||||
K(NMOS MOS3)
|
||||
X(INV
|
||||
N(1 I(VDD))
|
||||
N(2 I(VSS))
|
||||
N(3 I(A))
|
||||
N(4 I(Q))
|
||||
P(1 I(VDD))
|
||||
P(2 I(VSS))
|
||||
P(3 I(A))
|
||||
P(4 I(Q))
|
||||
D(1 PMOS
|
||||
I($1)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 1)
|
||||
T(G 3)
|
||||
T(D 4)
|
||||
)
|
||||
D(2 NMOS
|
||||
I($3)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0)
|
||||
E(AD 0)
|
||||
E(PS 0)
|
||||
E(PD 0)
|
||||
T(S 2)
|
||||
T(G 3)
|
||||
T(D 4)
|
||||
)
|
||||
)
|
||||
X(INV2
|
||||
N(1 I(VDD))
|
||||
N(2 I(VSS))
|
||||
N(3 I(A1))
|
||||
N(4 I(Q1))
|
||||
N(5 I(A2))
|
||||
N(6 I(Q2))
|
||||
P(1 I(VDD))
|
||||
P(2 I(VSS))
|
||||
P(3 I(A1))
|
||||
P(4 I(Q1))
|
||||
P(5 I(A2))
|
||||
P(6 I(Q2))
|
||||
X(1 INV I($1)
|
||||
P(0 1)
|
||||
P(1 2)
|
||||
P(2 3)
|
||||
P(3 4)
|
||||
)
|
||||
X(2 INV I($2)
|
||||
P(0 1)
|
||||
P(1 2)
|
||||
P(2 5)
|
||||
P(3 6)
|
||||
)
|
||||
)
|
||||
X(INVCHAIN
|
||||
N(1 I(VDD))
|
||||
N(2 I(VSS))
|
||||
N(3 I(A1))
|
||||
N(4 I(Q1))
|
||||
N(5 I(A2))
|
||||
N(6 I(Q2))
|
||||
N(7 I('1'))
|
||||
N(8 I('2'))
|
||||
P(1 I(VDD))
|
||||
P(2 I(VSS))
|
||||
P(3 I(A1))
|
||||
P(4 I(Q1))
|
||||
P(5 I(A2))
|
||||
P(6 I(Q2))
|
||||
X(1 INV2 I($2)
|
||||
P(0 1)
|
||||
P(1 2)
|
||||
P(2 3)
|
||||
P(3 7)
|
||||
P(4 7)
|
||||
P(5 4)
|
||||
)
|
||||
X(2 INV2 I($3)
|
||||
P(0 1)
|
||||
P(1 2)
|
||||
P(2 5)
|
||||
P(3 8)
|
||||
P(4 8)
|
||||
P(5 6)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
N(1 I(VDD))
|
||||
N(2 I(VSS))
|
||||
N(3 I(A))
|
||||
N(4 I('1'))
|
||||
N(5 I('3'))
|
||||
N(6 I('2'))
|
||||
N(7 I(Q))
|
||||
X(1 INVCHAIN I($1)
|
||||
P(0 1)
|
||||
P(1 2)
|
||||
P(2 3)
|
||||
P(3 4)
|
||||
P(4 4)
|
||||
P(5 5)
|
||||
)
|
||||
X(2 INV2 I($2)
|
||||
P(0 1)
|
||||
P(1 2)
|
||||
P(2 5)
|
||||
P(3 6)
|
||||
P(4 6)
|
||||
P(5 7)
|
||||
)
|
||||
)
|
||||
)
|
||||
Z(
|
||||
X(INV INV 1
|
||||
Z(
|
||||
N(3 3 1)
|
||||
N(4 4 1)
|
||||
N(2 1 1)
|
||||
N(1 2 1)
|
||||
P(2 2 1)
|
||||
P(3 3 1)
|
||||
P(1 0 1)
|
||||
P(0 1 1)
|
||||
D(2 2 1)
|
||||
D(1 1 1)
|
||||
)
|
||||
)
|
||||
X(INV2 INV2 1
|
||||
Z(
|
||||
N(2 3 1)
|
||||
N(3 5 1)
|
||||
N(4 4 1)
|
||||
N(5 6 1)
|
||||
N(1 1 1)
|
||||
N(6 2 1)
|
||||
P(1 2 1)
|
||||
P(2 4 1)
|
||||
P(3 3 1)
|
||||
P(4 5 1)
|
||||
P(0 0 1)
|
||||
P(5 1 1)
|
||||
X(2 1 1)
|
||||
X(1 2 1)
|
||||
)
|
||||
)
|
||||
X(INVCHAIN INVCHAIN 1
|
||||
L(
|
||||
M(W B('Matching nets OUT vs. Q1 from an ambiguous group of nets'))
|
||||
M(W B('Matching nets OUT2 vs. Q2 from an ambiguous group of nets'))
|
||||
M(I B('Matching nets $2 vs. 1 following an ambiguous match'))
|
||||
M(I B('Matching nets IN vs. A1 following an ambiguous match'))
|
||||
M(I B('Matching nets $1 vs. 2 following an ambiguous match'))
|
||||
M(I B('Matching nets IN2 vs. A2 following an ambiguous match'))
|
||||
)
|
||||
Z(
|
||||
N(2 7 1)
|
||||
N(1 8 1)
|
||||
N(3 3 1)
|
||||
N(4 5 1)
|
||||
N(6 4 W)
|
||||
N(7 6 W)
|
||||
N(8 1 1)
|
||||
N(5 2 1)
|
||||
P(0 2 1)
|
||||
P(1 4 1)
|
||||
P(3 3 1)
|
||||
P(4 5 1)
|
||||
P(5 0 1)
|
||||
P(2 1 1)
|
||||
X(2 1 1)
|
||||
X(1 2 1)
|
||||
)
|
||||
)
|
||||
X(TOP TOP 1
|
||||
Z(
|
||||
N(3 4 1)
|
||||
N(1 6 1)
|
||||
N(2 5 1)
|
||||
N(7 1 1)
|
||||
N(5 3 1)
|
||||
N(6 7 1)
|
||||
N(4 2 1)
|
||||
P(1 () 1)
|
||||
P(2 () 1)
|
||||
P(0 () 1)
|
||||
X(1 2 1)
|
||||
X(2 1 1)
|
||||
)
|
||||
)
|
||||
)
|
||||
Loading…
Reference in New Issue