WIP: added more test data, doc links

testdata/lvs/inv.lvs

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+
+source("inv.oas", "INVERTER")
+
+deep
+
+# Reports generated
+
+# LVS report to inv.lvsdb
+report_lvs("inv.lvsdb")
+
+# Write extracted netlist to inv_extracted.cir
+target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")
+
+# Drawing layers
+
+nwell       = input(1, 0)
+active      = input(2, 0)
+pplus       = input(3, 0)
+nplus       = input(4, 0)
+poly        = input(5, 0)
+contact     = input(6, 0)
+metal1      = input(7, 0)
+metal1_lbl  = labels(7, 1)
+via1        = input(8, 0)
+metal2      = input(9, 0)
+metal2_lbl  = labels(9, 1)
+
+# Bulk layer for terminal provisioning
+
+bulk        = polygon_layer
+
+# Computed layers
+
+active_in_nwell       = active & nwell
+pactive               = active_in_nwell & pplus
+pgate                 = pactive & poly
+psd                   = pactive - pgate
+
+active_outside_nwell  = active - nwell
+nactive               = active_outside_nwell & nplus
+ngate                 = nactive & poly
+nsd                   = nactive - ngate
+
+# Device extraction
+
+# PMOS transistor device extraction
+extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, 
+                                "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
+
+# NMOS transistor device extraction
+extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, 
+                                "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(psd,        contact)
+connect(nsd,        contact)
+connect(poly,       contact)
+connect(contact,    metal1)
+connect(metal1,     metal1_lbl)   # attaches labels
+connect(metal1,     via1)
+connect(via1,       metal2)
+connect(metal2,     metal2_lbl)   # attaches labels
+
+# Global
+connect_global(bulk,  "SUBSTRATE")
+connect_global(nwell, "NWELL")
+
+# Compare section
+
+schematic("inv.cir")
+
+compare
+

testdata/lvs/inv2.cir

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+
+* Simple CMOS inverer circuit 
+
+.SUBCKT INVERTER_WITH_DIODES VSS IN OUT VDD 
+Mp VDD IN OUT VDD PMOS W=1.5U L=0.25U
+Mn OUT IN VSS VSS NMOS W=0.9U L=0.25U
+.ENDS
+

testdata/lvs/inv2.lvs

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+
+source("inv.oas", "INVERTER_WITH_DIODES")
+
+deep
+
+# Reports generated
+
+# LVS report to inv.lvsdb
+report_lvs("inv.lvsdb")
+
+# Write extracted netlist to inv_extracted.cir
+target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")
+
+# Drawing layers
+
+nwell       = input(1, 0)
+active      = input(2, 0)
+pplus       = input(3, 0)
+nplus       = input(4, 0)
+poly        = input(5, 0)
+contact     = input(6, 0)
+metal1      = input(7, 0)
+metal1_lbl  = labels(7, 1)
+via1        = input(8, 0)
+metal2      = input(9, 0)
+metal2_lbl  = labels(9, 1)
+
+# Bulk layer for terminal provisioning
+
+bulk        = polygon_layer
+
+# Computed layers
+
+active_in_nwell       = active & nwell
+pactive               = active_in_nwell & pplus
+pgate                 = pactive & poly
+psd                   = pactive - pgate
+ntie                  = active_in_nwell & nplus
+
+active_outside_nwell  = active - nwell
+nactive               = active_outside_nwell & nplus
+ngate                 = nactive & poly
+nsd                   = nactive - ngate
+ptie                  = active_outside_nwell & pplus
+
+# Device extraction
+
+# PMOS transistor device extraction
+extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell, 
+                                "tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
+
+# NMOS transistor device extraction
+extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk, 
+                                "tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
+
+# Define connectivity for netlist extraction
+
+# Inter-layer
+connect(psd,        contact)
+connect(nsd,        contact)
+connect(poly,       contact)
+connect(ntie,       contact)
+connect(nwell,      ntie)
+connect(ptie,       contact)
+connect(contact,    metal1)
+connect(metal1,     metal1_lbl)   # attaches labels
+connect(metal1,     via1)
+connect(via1,       metal2)
+connect(metal2,     metal2_lbl)   # attaches labels
+
+# Global
+connect_global(bulk, "SUBSTRATE")
+connect_global(ptie, "SUBSTRATE")
+
+# Compare section
+
+schematic("inv2.cir")
+
+compare
+