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Issue #2360: Implemented name sorting by default (can be turned off) for 'make_top_level_pins'

This commit is contained in:
Matthias Koefferlein 2026-05-26 23:26:16 +02:00
parent 6e0d968058
commit 7d5f61db59
60 changed files with 97 additions and 13 deletions
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36
src/db/db/dbNetlist.cc
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@ -626,7 +626,26 @@ void Netlist::purge_devices ()
}
}
void Netlist::make_top_level_pins ()
namespace {
struct CompareNetByName
{
CompareNetByName (const db::Netlist *netlist)
: mp_netlist (netlist)
{ }
bool operator() (const db::Net *a, const db::Net *b)
{
return mp_netlist->normalize_name (a->name ()) < mp_netlist->normalize_name (b->name ());
}
private:
const db::Netlist *mp_netlist;
};
}
void Netlist::make_top_level_pins (bool sort_by_name)
{
size_t ntop = top_circuit_count ();
for (top_down_circuit_iterator c = begin_top_down (); c != end_top_down () && ntop > 0; ++c, --ntop) {
@ -635,14 +654,25 @@ void Netlist::make_top_level_pins ()
if (circuit->pin_count () == 0) {
std::vector<db::Net *> nets_for_pins;
// create pins for the named nets and connect them
for (Circuit::net_iterator n = circuit->begin_nets (); n != circuit->end_nets (); ++n) {
if (! n->name ().empty () && n->terminal_count () + n->subcircuit_pin_count () > 0) {
Pin pin = circuit->add_pin (n->name ());
circuit->connect_pin (pin.id (), n.operator-> ());
nets_for_pins.push_back (n.operator-> ());
}
}
if (sort_by_name) {
std::stable_sort (nets_for_pins.begin (), nets_for_pins.end (), CompareNetByName (this));
}
// create pins for the named nets and connect them
for (auto n = nets_for_pins.begin (); n != nets_for_pins.end (); ++n) {
Pin pin = circuit->add_pin ((*n)->name ());
circuit->connect_pin (pin.id (), *n);
}
}
}

2
src/db/db/dbNetlist.h
View File

@ -523,7 +523,7 @@ public:
* referenced by subcircuits) into pins. This method can be used before purge to
* avoid that purge will remove nets which are directly connecting to subcircuits.
*/
void make_top_level_pins ();
void make_top_level_pins (bool sort_by_name = true);
/**
* @brief Purge unused nets, circuits and subcircuits

7
src/db/db/gsiDeclDbNetlist.cc
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@ -2240,11 +2240,14 @@ Class<db::Netlist> decl_dbNetlist ("db", "Netlist",
"For example, serial or parallel resistors can be combined into "
"a single resistor.\n"
) +
gsi::method ("make_top_level_pins", &db::Netlist::make_top_level_pins,
gsi::method ("make_top_level_pins", &db::Netlist::make_top_level_pins, gsi::arg ("sorted_by_name", true),
"@brief Creates pins for top-level circuits.\n"
"This method will turn all named nets of top-level circuits (such that are not "
"referenced by subcircuits) into pins. This method can be used before purge to "
"avoid that purge will remove nets which are directly connecting to subcircuits."
"avoid that purge will remove nets which are directly connecting to subcircuits.\n"
"\n"
"Starting from version 0.30.9, the pins will be sorted by name by default. Sorting can be "
"disabled by setting \\sorted_by_name to false for backward compatibility."
) +
gsi::method ("purge", &db::Netlist::purge,
"@brief Purge unused nets, circuits and subcircuits.\n"

2
src/db/unit_tests/dbLayoutToNetlistWriterTests.cc
View File

@ -163,7 +163,7 @@ TEST(1_WriterBasic)
rpoly_lbl.reset (0);
l2n.extract_netlist ();
l2n.netlist ()->make_top_level_pins ();
l2n.netlist ()->make_top_level_pins (false);
l2n.netlist ()->purge ();
std::string path = tmp_file ("tmp_l2nwriter_1.txt");

1
testdata/lvs/bbdevices1b.lvs vendored
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@ -70,6 +70,7 @@ connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/bbdevices2b.lvs vendored
View File

@ -70,6 +70,7 @@ connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/bbdevices4b.lvs vendored
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@ -70,6 +70,7 @@ connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/bbdevices5b.lvs vendored
View File

@ -70,6 +70,7 @@ connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/bbdevices6b.lvs vendored
View File

@ -70,6 +70,7 @@ connect(layer.btp, layer.bm1)
connect(layer.bdpPad, layer.bm1)
blank_circuit("*TEST")
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/custom_compare.lvs vendored
View File

@ -63,6 +63,7 @@ end
netlist.device_class_by_name("RES").equal_parameters = ResistorComparator::new()
# Netlist normalization
netlist.make_top_level_pins(false)
netlist.simplify
# Hierarchy alignment (flatten out unmatched cells)

2
testdata/lvs/double_height.cir vendored
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@ -1,6 +1,6 @@
* Extracted by KLayout
.SUBCKT INVCHAIN IN OUT VSS VDD
.SUBCKT INVCHAIN IN OUT VDD VSS
X$1 VDD IN \$1 \$1 OUT VSS INV2
.ENDS INVCHAIN

1
testdata/lvs/double_height.lvs vendored
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@ -123,6 +123,7 @@ connect_implicit("INV2", "VSS")
# Compare section
# NOTE: indirectly tests "make_top_level_pins" with name sorting (#2360)
netlist.simplify
align

4
testdata/lvs/double_height.lvsdb vendored
View File

@ -185,8 +185,8 @@ J(
)
P(2 I(IN))
P(3 I(OUT))
P(4 I(VSS))
P(5 I(VDD))
P(4 I(VSS))
X(1 INV2 Y(0 0)
P(0 5)
P(1 2)
@ -318,8 +318,8 @@ Z(
N(4 2 1)
P(0 () 1)
P(1 () 1)
P(3 () 1)
P(2 () 1)
P(3 () 1)
X(1 1 1)
)
)

1
testdata/lvs/double_height2.lvs vendored
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@ -130,6 +130,7 @@ connect_implicit("DOESNOTEXIST", "DOESNOTEXIST")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/double_height2_texts.lvs vendored
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@ -130,6 +130,7 @@ connect_implicit("DOESNOTEXIST", "DOESNOTEXIST")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/enable_wl1.lvs vendored
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@ -47,6 +47,7 @@ connect(contact, metal1_not_res)
connect(metal1_not_res, metal1_lbl)
align
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/enable_wl2.lvs vendored
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@ -28,6 +28,7 @@ connect(contact, metal1_not_res)
connect(metal1_not_res, metal1_lbl)
align
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/enable_wl3.lvs vendored
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@ -28,6 +28,7 @@ connect(contact, metal1_not_res)
connect(metal1_not_res, metal1_lbl)
align
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/flag_missing_ports.lvs vendored
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@ -68,6 +68,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/floating.lvs vendored
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@ -68,6 +68,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/invchain_cheat.lvs vendored
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@ -123,6 +123,7 @@ connect_global(bulk, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/layer_names.lvs vendored
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@ -96,6 +96,7 @@ ok || raise("ptie layer already used - this is an error")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/must_connect1.lvs vendored
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@ -132,6 +132,7 @@ connect_implicit("INVCHAIN", "VDD")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/must_connect1_tl.lvs vendored
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@ -136,6 +136,7 @@ connect_implicit("INVCHAIN", "VDD")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/must_connect2.lvs vendored
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@ -134,6 +134,7 @@ connect_global(bulk, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/must_connect3.lvs vendored
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@ -134,6 +134,7 @@ connect_global(bulk, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/nand2_split_gate.lvs vendored
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@ -76,6 +76,7 @@ connect_global(ptie, "SUBSTRATE")
netlist
join_symmetric_nets("*")
netlist.make_top_level_pins(false)
netlist.simplify
# Compare section

1
testdata/lvs/nand2_split_gate_early.lvs vendored
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@ -77,6 +77,7 @@ connect_global(ptie, "SUBSTRATE")
# Extract, simplify
netlist
netlist.make_top_level_pins(false)
netlist.simplify
# Compare section

1
testdata/lvs/res_combine1.lvs vendored
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@ -93,6 +93,7 @@ schematic.simplify
# Netlist vs. netlist
align
netlist.make_top_level_pins(false)
netlist.simplify
no_lvs_hints
compare

1
testdata/lvs/res_combine2.lvs vendored
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@ -92,6 +92,7 @@ schematic.simplify
# Netlist vs. netlist
align
netlist.make_top_level_pins(false)
netlist.simplify
no_lvs_hints
compare

1
testdata/lvs/res_combine3.lvs vendored
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@ -87,6 +87,7 @@ schematic.simplify
# Netlist vs. netlist
align
netlist.make_top_level_pins(false)
netlist.simplify
no_lvs_hints
compare

1
testdata/lvs/ringo_device_subcircuits.lvs vendored
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@ -120,6 +120,7 @@ same_device_classes("PMOS", $change_case ? "xpMos" : "XPMOS")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_layout_var.lvs vendored
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@ -72,6 +72,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_mixed_hierarchy.lvs vendored
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@ -68,6 +68,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
align

1
testdata/lvs/ringo_simple.lvs vendored
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@ -68,6 +68,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

2
testdata/lvs/ringo_simple_blackboxing.lvs vendored
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@ -78,7 +78,7 @@ schematic.blank_circuit("INVX1")
schematic.blank_circuit("INVX2")
schematic.blank_circuit("ND2X1")
netlist.make_top_level_pins
netlist.make_top_level_pins(false)
netlist.purge
netlist.combine_devices
netlist.purge_nets

2
testdata/lvs/ringo_simple_blackboxing_netter.lvs vendored
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@ -76,7 +76,7 @@ connect_global(ptie, "SUBSTRATE")
netlist.flatten_circuit("INVCHAIN")
netlist.make_top_level_pins
netlist.make_top_level_pins(false)
netlist.purge
netlist.combine_devices
netlist.purge_nets

1
testdata/lvs/ringo_simple_compare2.lvs vendored
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@ -68,6 +68,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_device_scaling.lvs vendored
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@ -70,6 +70,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_dmos.lvs vendored
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@ -75,6 +75,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_dmos_fixed.lvs vendored
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@ -77,6 +77,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_dummy_device.lvs vendored
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@ -68,6 +68,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_implicit_connections.lvs vendored
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@ -72,6 +72,7 @@ connect_implicit("VDD")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_io.lvs vendored
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@ -69,6 +69,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_io2.lvs vendored
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@ -102,6 +102,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_net_and_circuit_equivalence.lvs vendored
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@ -76,6 +76,7 @@ same_circuits("INV", $change_case ? "invX1" : "INVX1")
same_circuits("DOESNOTEXIST", "DOESNOTEXIST2")
same_nets("DOESNOTEXIST", "ENABLE", "DOESNOTEXIST2", "ENABLE")
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_pin_swapping.lvs vendored
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@ -73,6 +73,7 @@ connect_global(ptie, "SUBSTRATE")
equivalent_pins("DOESNOTEXIST", 4, 5)
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_same_device_classes.lvs vendored
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@ -91,6 +91,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
same_device_classes("NM", "NMOS")

2
testdata/lvs/ringo_simple_simplification.lvs vendored
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@ -70,7 +70,7 @@ connect_global(ptie, "SUBSTRATE")
netlist.flatten_circuit("INVCHAIN")
netlist.make_top_level_pins
netlist.make_top_level_pins(false)
netlist.purge
netlist.combine_devices
netlist.purge_nets

1
testdata/lvs/ringo_simple_simplification_with_align.lvs vendored
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@ -70,6 +70,7 @@ connect_global(ptie, "SUBSTRATE")
align
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_with_tol.lvs vendored
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@ -73,6 +73,7 @@ tolerance("PMOS", "W", 0.01, 0.1) # relative + absolute
tolerance("NMOS", "L", :absolute => 0.01)
tolerance("NMOS", "W", :relative => 0.07)
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/ringo_simple_with_tol_early.lvs vendored
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@ -73,6 +73,7 @@ connect_global(ptie, "SUBSTRATE")
# Compare section
netlist.make_top_level_pins(false)
netlist.simplify
compare

1
testdata/lvs/soft_connect1.lvs vendored
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@ -87,6 +87,7 @@ soft_connect_global(ptie, "SUBSTRATE")
# Netlist section (NOTE: we only check log here)
netlist
netlist.make_top_level_pins(false)
netlist.simplify

1
testdata/lvs/soft_connect1a.lvs vendored
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@ -87,6 +87,7 @@ soft_connect_global(ptie, "SUBSTRATE")
# Netlist section (NOTE: we only check log here)
netlist
netlist.make_top_level_pins(false)
netlist.simplify

1
testdata/lvs/soft_connect2.lvs vendored
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@ -87,6 +87,7 @@ soft_connect_global(ptie, "SUBSTRATE")
# Netlist section (NOTE: we only check log here)
netlist
netlist.make_top_level_pins(false)
netlist.simplify

1
testdata/lvs/soft_connect3.lvs vendored
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@ -87,6 +87,7 @@ soft_connect_global(ptie, "SUBSTRATE")
# Netlist section (NOTE: we only check log here)
netlist
netlist.make_top_level_pins(false)
netlist.simplify

1
testdata/lvs/soft_connect4.lvs vendored
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@ -88,6 +88,7 @@ soft_connect_global(ptie, "SUBSTRATE")
# for debugging: _make_soft_connection_diodes(true)
netlist
netlist.make_top_level_pins(false)
netlist.simplify

1
testdata/lvs/soft_connect5.lvs vendored
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@ -88,6 +88,7 @@ soft_connect_global(ptie, "SUBSTRATE")
# for debugging: _make_soft_connection_diodes(true)
netlist
netlist.make_top_level_pins(false)
netlist.simplify

1
testdata/lvs/soft_connect6.lvs vendored
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@ -88,6 +88,7 @@ soft_connect_global(ptie, "SUBSTRATE")
# for debugging: _make_soft_connection_diodes(true)
netlist
netlist.make_top_level_pins(false)
netlist.simplify

1
testdata/lvs/split_substrate.lvs vendored
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@ -102,6 +102,7 @@ connect_global(iosub, "IOSUB")
# for debugging: _make_soft_connection_diodes(true)
netlist
netlist.make_top_level_pins(false)
netlist.simplify