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klayout
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Updated tests

This commit is contained in:
Matthias Koefferlein 2023-09-24 19:01:30 +02:00
parent 1b4c81ac7b
commit 6412c534b8
16 changed files with 37 additions and 31 deletions
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4
src/db/db/dbLayoutToNetlist.cc
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@ -476,11 +476,11 @@ void LayoutToNetlist::check_must_connect (const db::Circuit &c, const db::Net &a
}
} else {
if (a.expanded_name () == b.expanded_name ()) {
db::LogEntryData warn (db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s must be connected further up in the hierarchy. This is an error at the chip top level.")), a.expanded_name ()));
db::LogEntryData warn (db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s must be connected further up in the hierarchy - this is an error at the chip top level")), a.expanded_name ()));
warn.set_cell_name (c.name ());
log_entry (warn);
} else {
db::LogEntryData warn (db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s and %s must be connected further up in the hierarchy. This is an error at the chip top level.")), a.expanded_name (), b.expanded_name ()));
db::LogEntryData warn (db::Warning, tl::sprintf (tl::to_string (tr ("Must-connect nets %s and %s must be connected further up in the hierarchy - this is an error at the chip top level")), a.expanded_name (), b.expanded_name ()));
warn.set_cell_name (c.name ());
log_entry (warn);
}

4
src/db/db/dbLayoutToNetlistWriter.cc
View File

@ -205,7 +205,7 @@ template <class Keys>
void std_writer_impl<Keys>::write_log_entry (TokenizedOutput &stream, const LogEntryData &le)
{
stream << severity_to_s (le.severity ());
stream << message_to_s (le.to_string ());
stream << message_to_s (le.message ());
if (! le.cell_name ().empty ()) {
TokenizedOutput (stream, Keys::cell_key, true) << tl::to_word_or_quoted_string (le.cell_name ());
@ -220,7 +220,7 @@ void std_writer_impl<Keys>::write_log_entry (TokenizedOutput &stream, const LogE
}
if (le.geometry () != db::DPolygon ()) {
TokenizedOutput o (stream, Keys::polygon_key);
TokenizedOutput o (stream, Keys::polygon_key, true);
o << tl::to_word_or_quoted_string (le.geometry ().to_string ());
}
}

12
src/db/db/dbLayoutVsSchematicWriter.cc
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@ -203,8 +203,10 @@ void std_writer_impl<Keys>::write (TokenizedOutput &stream, const db::NetlistCro
o << endl;
for (auto l = xref->other_log_entries ().begin (); l != xref->other_log_entries ().end (); ++l) {
TokenizedOutput to (o, Keys::log_entry_key, true);
this->write_log_entry (to, *l);
{
TokenizedOutput to (o, Keys::log_entry_key, true);
this->write_log_entry (to, *l);
}
o << endl;
}
@ -225,8 +227,10 @@ void std_writer_impl<Keys>::write (TokenizedOutput &stream, const db::NetlistCro
o << endl;
for (auto l = pcd->log_entries.begin (); l != pcd->log_entries.end (); ++l) {
TokenizedOutput to (o, Keys::log_entry_key, true);
this->write_log_entry (to, *l);
{
TokenizedOutput to (o, Keys::log_entry_key, true);
this->write_log_entry (to, *l);
}
o << endl;
}

8
src/db/db/dbLog.cc
View File

@ -170,12 +170,14 @@ LogEntryData::to_string () const
}
}
res += message ();
if (m_cell_name != 0) {
res += tl::to_string (tr (", in cell: ")) + cell_name ();
res += tl::to_string (tr ("In cell "));
res += cell_name ();
res += ": ";
}
res += message ();
if (! m_geometry.box ().empty ()) {
res += tl::to_string (tr (", shape: ")) + m_geometry.to_string ();
}

6
testdata/lvs/double_height2.lvsdb vendored
View File

@ -27,9 +27,9 @@ J(
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets GND from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(W B('Must-connect nets R from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(E B('Must-connect nets R from circuit INV2 are not connected in INVCHAIN'))
H(W B('Must-connect nets GND must be connected further up in the hierarchy - this is an error at the chip top level') C(INVCHAIN))
H(W B('Must-connect nets R must be connected further up in the hierarchy - this is an error at the chip top level') C(INVCHAIN))
H(E B('Must-connect nets R are not connected in INVCHAIN') C(INV2))
K(PMOS MOS3)
K(NMOS MOS3)
D(D$PMOS PMOS

6
testdata/lvs/double_height2_texts.lvsdb vendored
View File

@ -27,9 +27,9 @@ J(
C(l2 l6 l2)
C(l5 l6 l5)
G(l14 SUBSTRATE)
H(W B('Must-connect nets GND from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(W B('Must-connect nets R from circuit INVCHAIN must be connected further up in the hierarchy. This is an error at the chip top level.'))
H(E B('Must-connect nets R from circuit INV2 are not connected in INVCHAIN'))
H(W B('Must-connect nets GND must be connected further up in the hierarchy - this is an error at the chip top level') C(INVCHAIN))
H(W B('Must-connect nets R must be connected further up in the hierarchy - this is an error at the chip top level') C(INVCHAIN))
H(E B('Must-connect nets R are not connected in INVCHAIN') C(INV2))
K(PMOS MOS3)
K(NMOS MOS3)
D(D$PMOS PMOS

2
testdata/lvs/ringo_simple_implicit_connections.lvsdb.1 vendored
View File

@ -39,7 +39,7 @@ layout(
global(l10 SUBSTRATE)
# Log entries
message(warning description('Must-connect nets VDD from circuit RINGO must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets VDD must be connected further up in the hierarchy - this is an error at the chip top level') cell(RINGO))
# Device class section
class(PMOS MOS4)

2
testdata/lvs/test_22a.lvsdb.1 vendored
View File

@ -71,7 +71,7 @@ layout(
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at the chip top level') cell(SP6TArray_2X4))
# Device class section
class(active_res RES)

2
testdata/lvs/test_22a.lvsdb.2 vendored
View File

@ -71,7 +71,7 @@ layout(
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at the chip top level') cell(SP6TArray_2X4))
# Device class section
class(active_res RES)

2
testdata/lvs/test_22b.lvsdb.1 vendored
View File

@ -71,7 +71,7 @@ layout(
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at the chip top level') cell(SP6TArray_2X4))
# Device class section
class(active_res RES)

2
testdata/lvs/test_22b.lvsdb.2 vendored
View File

@ -71,7 +71,7 @@ layout(
global(l6 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at the chip top level') cell(SP6TArray_2X4))
# Device class section
class(active_res RES)

2
testdata/lvs/test_22c.lvsdb.1 vendored
View File

@ -71,7 +71,7 @@ layout(
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at the chip top level') cell(SP6TArray_2X4))
# Device class section
class(active_res RES)

2
testdata/lvs/test_22c.lvsdb.2 vendored
View File

@ -71,7 +71,7 @@ layout(
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at the chip top level') cell(SP6TArray_2X4))
# Device class section
class(active_res RES)

2
testdata/lvs/test_22d.lvsdb.1 vendored
View File

@ -71,7 +71,7 @@ layout(
global(l1 vss)
# Log entries
message(warning description('Must-connect nets vdd from circuit SP6TArray_2X4 must be connected further up in the hierarchy. This is an error at the chip top level.'))
message(warning description('Must-connect nets vdd must be connected further up in the hierarchy - this is an error at the chip top level') cell(SP6TArray_2X4))
# Device class section
class(active_res RES)

10
testdata/ruby/dbNetlist.rb vendored
View File

@ -1120,11 +1120,11 @@ END
c.join_nets(c.net_by_name("IN"), c.net_by_name("OUT"))
assert_equal(nl.to_s, <<"END")
circuit INV2 (IN=IN,$2=$2,OUT=IN,$4=$4,$5=$5);
subcircuit PTRANS SC1 ($1=$5,$2=$2,$3=IN);
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3=IN);
subcircuit PTRANS SC3 ($1=$5,$2=IN,$3=$2);
subcircuit NTRANS SC4 ($1=$4,$2=IN,$3=$2);
circuit INV2 ('IN,OUT'='IN,OUT',$2=$2,$3=$4,$4=$5);
subcircuit PTRANS SC1 ($1=$5,$2=$2,$3='IN,OUT');
subcircuit NTRANS SC2 ($1=$4,$2=$2,$3='IN,OUT');
subcircuit PTRANS SC3 ($1=$5,$2='IN,OUT',$3=$2);
subcircuit NTRANS SC4 ($1=$4,$2='IN,OUT',$3=$2);
end;
circuit PTRANS ($1=$1,$2=$2,$3=$3);
device PMOS $1 (S=$1,G=$3,D=$2) (L=0.25,W=0.95,AS=0,AD=0,PS=0,PD=0);

2
testdata/ruby/dbNetlistDeviceExtractors.rb vendored
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@ -27,7 +27,7 @@ class DBNetlistExtractorTests_TestClass < TestBase
def test_1_Error
err = RBA::NetlistDeviceExtractorError::new
err = RBA::LogEntryData::new
err.message = "MSG"
err.cell_name = "Cell"