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WIP: unit tests updated

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This commit is contained in:
Matthias Koefferlein
2019-06-22 10:15:32 +02:00
parent 847f60947d
commit 46dafd50ea
10 changed files with 68 additions and 31 deletions
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testdata/algo/bipolar_devices_nets.gds
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testdata/algo/lvs_test1_au.lvsdb
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+4 -2
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@@ -799,7 +799,8 @@ reference(
# Devices and their connections
device(1 PMOS
name($1) param(L 0.25)
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@@ -811,7 +812,8 @@ reference(
terminal(B 1)
)
device(2 NMOS
name($3) param(L 0.25)
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
testdata/algo/lvs_test1b_au.lvsdb
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+4 -2
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@@ -799,7 +799,8 @@ reference(
# Devices and their connections
device(1 PMOS
name($1) param(L 0.25)
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@@ -811,7 +812,8 @@ reference(
terminal(B 1)
)
device(2 NMOS
name($3) param(L 0.25)
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
testdata/algo/lvs_test2_au.lvsdb
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+4 -2
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@@ -799,7 +799,8 @@ reference(
# Devices and their connections
device(1 PMOS
name($1) param(L 0.25)
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@@ -811,7 +812,8 @@ reference(
terminal(B 1)
)
device(2 NMOS
name($3) param(L 0.25)
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
testdata/algo/lvs_test2b_au.lvsdb
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+4 -2
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@@ -799,7 +799,8 @@ reference(
# Devices and their connections
device(1 PMOS
name($1) param(L 0.25)
name($1)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
@@ -811,7 +812,8 @@ reference(
terminal(B 1)
)
device(2 NMOS
name($3) param(L 0.25)
name($3)
param(L 0.25)
param(W 3.5)
param(AS 1.4)
param(AD 1.4)
testdata/ruby/dbNetlist.rb
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+4
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@@ -829,6 +829,7 @@ circuit NTRANS ($1=$1,$2=$2,$3=$3);
end;
END
nl3 = nl2.dup
nl2.flatten_circuit(nl2.circuit_by_name("PTRANS"))
nl2.flatten_circuit(nl2.circuit_by_name("NTRANS"))
@@ -841,6 +842,9 @@ circuit INV2 (IN=IN,$2=$2,OUT=OUT,$4=$4,$5=$5);
end;
END
nl3.flatten_circuit("{N,P}TRANS")
assert_equal(nl3.to_s, nl2.to_s)
end
end
testdata/ruby/dbNetlistDeviceClasses.rb
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+9 -6
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@@ -484,6 +484,7 @@ END
d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PE, 12.0)
d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PB, 13.0)
d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_PC, 14.0)
d1.set_parameter(RBA::DeviceClassBJT3Transistor::PARAM_NE, 2.0)
d2 = circuit.create_device(cls, "d2")
d2.set_parameter("AE", 2.0)
d2.set_parameter("AB", 3.0)
@@ -491,6 +492,7 @@ END
d2.set_parameter("PE", 13.0)
d2.set_parameter("PB", 14.0)
d2.set_parameter("PC", 15.0)
d2.set_parameter("NE", 3.0)
pin_a = circuit.create_pin ("A")
pin_b = circuit.create_pin ("B")
@@ -513,8 +515,8 @@ END
assert_equal(nl.to_s, <<END)
circuit '' (A=n1,B=n2,C=n3);
device '' d1 (C=n1,B=n3,E=n2) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14);
device '' d2 (C=n1,B=n3,E=n2) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15);
device '' d1 (C=n1,B=n3,E=n2) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14,NE=2);
device '' d2 (C=n1,B=n3,E=n2) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15,NE=3);
end;
END
@@ -523,7 +525,7 @@ END
assert_equal(nl.to_s, <<END)
circuit '' (A=n1,B=n2,C=n3);
device '' d1 (C=n1,B=n3,E=n2) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29);
device '' d1 (C=n1,B=n3,E=n2) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29,NE=5);
end;
END
@@ -553,6 +555,7 @@ END
d2.set_parameter("PE", 13.0)
d2.set_parameter("PB", 14.0)
d2.set_parameter("PC", 15.0)
d2.set_parameter("NE", 2.0)
pin_a = circuit.create_pin ("A")
pin_b = circuit.create_pin ("B")
@@ -581,8 +584,8 @@ END
assert_equal(nl.to_s, <<END)
circuit '' (A=n1,B=n2,C=n3,D=n4);
device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14);
device '' d2 (C=n1,B=n3,E=n2,S=n4) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15);
device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=1,PE=12,AB=2,PB=13,AC=3,PC=14,NE=1);
device '' d2 (C=n1,B=n3,E=n2,S=n4) (AE=2,PE=13,AB=3,PB=14,AC=4,PC=15,NE=2);
end;
END
@@ -591,7 +594,7 @@ END
assert_equal(nl.to_s, <<END)
circuit '' (A=n1,B=n2,C=n3,D=n4);
device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29);
device '' d1 (C=n1,B=n3,E=n2,S=n4) (AE=3,PE=25,AB=5,PB=27,AC=7,PC=29,NE=3);
end;
END