mirror of https://github.com/KLayout/klayout.git
More tests
This commit is contained in:
Matthias Koefferlein
parent
917439b84e
commit
10cf9c0bb6
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@ -302,20 +302,37 @@ TEST(40_DeviceExtractorErrors)
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}
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// Basic soft connection
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TEST(50_SoftConnection)
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TEST(50_BasicSoftConnection)
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{
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run_test (_this, "soft_connect1", "soft_connect1.gds", true, false /*no LVS*/);
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}
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// No errors
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TEST(51_SoftConnection)
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TEST(51_SoftConnectionNoErrors)
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{
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run_test (_this, "soft_connect2", "soft_connect2.gds", true, false /*no LVS*/);
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}
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// Simple hierarchy
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TEST(52_SoftConnection)
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TEST(52_SoftConnectionSimpleHierarchy)
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{
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run_test (_this, "soft_connect3", "soft_connect3.gds", true, false /*no LVS*/);
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}
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// Soft connected nets from different subcircuits
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TEST(53_SoftConnectionFromSubcircuits)
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{
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run_test (_this, "soft_connect4", "soft_connect4.gds", true, false /*no LVS*/);
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}
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// Soft connected nets from different subcircuits (propagated)
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TEST(54_SoftConnectionFromSubcircuits2)
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{
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run_test (_this, "soft_connect5", "soft_connect5.gds", true, false /*no LVS*/);
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}
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// Level 2 soft connection
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TEST(55_SoftConnectionSecondLevel)
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{
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run_test (_this, "soft_connect6", "soft_connect6.gds", true, false /*no LVS*/);
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}
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@ -0,0 +1,192 @@
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#%l2n-klayout
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W(TOP)
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U(0.001)
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L(l3 '1/0')
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L(l4 '3/0')
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L(l15 '3/1')
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L(l8 '4/0')
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L(l11 '5/0')
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L(l12 '6/0')
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L(l16 '6/1')
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L(l13 '7/0')
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L(l14 '8/0')
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L(l17)
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L(l7)
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L(l10)
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L(l2)
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L(l9)
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L(l6)
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C(l3 l3 l10)
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C(l4 l4 l15 l11)
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C(l15 l4 l15)
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C(l8 l8 l12 l10 l2 l9 l6)
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CS(l8 l10 l2 l9 l6)
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C(l11 l4 l11 l12)
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CS(l11 l4)
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C(l12 l8 l11 l12 l16 l13)
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C(l16 l12 l16)
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C(l13 l12 l13 l14)
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C(l14 l13 l14 l17)
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C(l17 l14 l17)
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C(l7 l7)
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C(l10 l3 l8 l10)
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CS(l10 l3)
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C(l2 l8 l2)
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C(l9 l8 l9)
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C(l6 l8 l6)
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G(l7 SUBSTRATE)
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G(l9 SUBSTRATE)
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GS(l9 SUBSTRATE)
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H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
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H(B('\tPartial net #1: TOP/INV[r0 3,1.6]:$1 - $2') C(TOP) Q('(1.5,3.95;1.5,4.85;5.3,4.85;5.3,3.95)'))
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H(B('\tPartial net #2: TOP/INV[r0 7.7,1.6]:$2 - $2') C(TOP) Q('(6.2,3.95;6.2,4.85;10,4.85;10,3.95)'))
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H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
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H(B('\tPartial net #1: TOP/INV[r0 3,1.6]:$1 - $1') C(TOP) Q('(1.5,1.15;1.5,2.05;5.3,2.05;5.3,1.15)'))
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H(B('\tPartial net #2: TOP/INV[r0 7.7,1.6]:$2 - $1') C(TOP) Q('(6.2,1.15;6.2,2.05;10,2.05;10,1.15)'))
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K(PMOS MOS4)
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K(NMOS MOS4)
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D(D$PMOS PMOS
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T(S
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R(l2 (-900 -475) (775 950))
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)
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T(G
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R(l4 (-125 -475) (250 950))
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)
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T(D
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R(l2 (125 -475) (775 950))
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)
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T(B
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R(l3 (-125 -475) (250 950))
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)
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)
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D(D$NMOS NMOS
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T(S
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R(l6 (-900 -475) (775 950))
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)
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T(G
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R(l4 (-125 -475) (250 950))
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)
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T(D
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R(l6 (125 -475) (775 950))
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)
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T(B
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R(l7 (-125 -475) (250 950))
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)
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)
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X(INV
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R((-1500 -800) (3800 4600))
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N(1 I(SUBSTRATE)
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R(l8 (1700 100) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l8 (-1610 -210) (220 220))
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R(l8 (-220 180) (220 220))
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R(l12 (890 -760) (800 900))
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R(l12 (-1980 -830) (360 760))
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R(l13 (-305 -705) (250 250))
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R(l13 (-250 150) (250 250))
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R(l13 (1175 -225) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l14 (-3400 -350) (3000 900))
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R(l14 (-200 -900) (1000 900))
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R(l6 (-2175 -925) (775 950))
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)
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N(2
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R(l3 (-1500 1800) (3000 2000))
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R(l3 (-200 -2000) (1000 2000))
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R(l8 (-2010 -1310) (220 220))
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R(l8 (-220 180) (220 220))
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R(l8 (1190 -210) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l12 (-1680 -280) (360 760))
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R(l12 (820 -830) (800 900))
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R(l13 (-1925 -775) (250 250))
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R(l13 (-250 150) (250 250))
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R(l13 (1175 -225) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l14 (-3400 -350) (3000 900))
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R(l14 (-200 -900) (1000 900))
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R(l10 (-700 -950) (400 1000))
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R(l2 (-1875 -975) (775 950))
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)
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N(3
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R(l4 (-125 -250) (250 2500))
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R(l4 (-250 -3050) (250 1600))
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R(l4 (-250 1200) (250 1600))
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)
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N(4
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R(l8 (-510 -310) (220 220))
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R(l8 (-220 180) (220 220))
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R(l8 (-220 2180) (220 220))
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R(l8 (-220 180) (220 220))
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R(l12 (-290 -3530) (360 2840))
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R(l12 (-360 -2800) (360 760))
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R(l12 (-360 2040) (360 760))
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R(l2 (-680 -855) (775 950))
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R(l6 (-775 -3750) (775 950))
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)
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P(2)
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P(3)
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P(4)
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P(1 I(SUBSTRATE))
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D(1 D$PMOS
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Y(0 2800)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 4)
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T(G 3)
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T(D 2)
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T(B 2)
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)
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D(2 D$NMOS
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Y(0 0)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 4)
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T(G 3)
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T(D 1)
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T(B 1)
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)
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)
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X(TOP
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R((1500 800) (9080 4600))
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N(1
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R(l4 (2920 2600) (3980 400))
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R(l11 (-300 -300) (200 200))
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R(l12 (-300 -300) (690 400))
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)
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N(2 I(A)
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R(l4 (7700 2600) (2880 400))
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R(l15 (-2380 -200) (0 0))
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)
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N(3 I(Q)
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R(l12 (1810 2600) (690 400))
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R(l16 (-400 -200) (0 0))
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)
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N(4
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R(l3 (4000 3400) (2700 2000))
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)
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N(5 I(SUBSTRATE))
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P(2 I(A))
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P(3 I(Q))
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P(5 I(SUBSTRATE))
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X(1 INV Y(3000 1600)
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P(0 4)
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P(1 1)
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P(2 3)
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P(3 5)
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)
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X(2 INV Y(7700 1600)
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P(0 4)
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P(1 2)
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P(2 1)
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P(3 5)
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)
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)
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@ -0,0 +1,13 @@
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* Extracted by KLayout
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.SUBCKT TOP A Q VDD SUBSTRATE|VSS
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X$1 SUBSTRATE|VSS VDD \$1 Q INV
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X$2 SUBSTRATE|VSS VDD A \$1 INV
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.ENDS TOP
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.SUBCKT INV SUBSTRATE \$2 \$4 \$5
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M$1 \$2 \$4 \$5 \$2 PMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P PS=3.45U
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+ PD=3.45U
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M$2 SUBSTRATE \$4 \$5 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
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+ PS=3.45U PD=3.45U
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.ENDS INV
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Binary file not shown.
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@ -0,0 +1,196 @@
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#%l2n-klayout
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W(TOP)
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U(0.001)
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L(l3 '1/0')
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L(l4 '3/0')
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L(l15 '3/1')
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L(l8 '4/0')
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L(l11 '5/0')
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L(l12 '6/0')
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L(l16 '6/1')
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L(l13 '7/0')
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L(l14 '8/0')
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L(l17 '8/1')
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L(l7)
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L(l10)
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L(l2)
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L(l9)
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L(l6)
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C(l3 l3 l10)
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C(l4 l4 l15 l11)
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C(l15 l4 l15)
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C(l8 l8 l12 l10 l2 l9 l6)
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CS(l8 l10 l2 l9 l6)
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C(l11 l4 l11 l12)
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CS(l11 l4)
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C(l12 l8 l11 l12 l16 l13)
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C(l16 l12 l16)
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C(l13 l12 l13 l14)
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C(l14 l13 l14 l17)
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C(l17 l14 l17)
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C(l7 l7)
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C(l10 l3 l8 l10)
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CS(l10 l3)
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C(l2 l8 l2)
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C(l9 l8 l9)
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C(l6 l8 l6)
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G(l7 SUBSTRATE)
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G(l9 SUBSTRATE)
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GS(l9 SUBSTRATE)
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H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
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H(B('\tPartial net #1: TOP - VDD') C(TOP) Q('(1.5,3.95;1.5,4.85;5.3,4.85;5.3,3.95)'))
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H(B('\tPartial net #2: TOP - $I7') C(TOP) Q('(6.2,3.95;6.2,4.85;10,4.85;10,3.95)'))
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H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
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H(B('\tPartial net #1: TOP - VSS') C(TOP) Q('(1.5,1.15;1.5,2.05;5.3,2.05;5.3,1.15)'))
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H(B('\tPartial net #2: TOP - $I6') C(TOP) Q('(6.2,1.15;6.2,2.05;10,2.05;10,1.15)'))
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K(PMOS MOS4)
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K(NMOS MOS4)
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D(D$PMOS PMOS
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T(S
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R(l2 (-900 -475) (775 950))
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)
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T(G
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R(l4 (-125 -475) (250 950))
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)
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T(D
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R(l2 (125 -475) (775 950))
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)
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T(B
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R(l3 (-125 -475) (250 950))
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)
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)
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D(D$NMOS NMOS
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T(S
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R(l6 (-900 -475) (775 950))
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)
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T(G
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R(l4 (-125 -475) (250 950))
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)
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T(D
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R(l6 (125 -475) (775 950))
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)
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T(B
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R(l7 (-125 -475) (250 950))
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)
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)
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X(INV
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R((-1500 -800) (3800 4600))
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N(1 I(SUBSTRATE)
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R(l8 (1700 100) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l8 (-1610 -210) (220 220))
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R(l8 (-220 180) (220 220))
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R(l12 (890 -760) (800 900))
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R(l12 (-1980 -830) (360 760))
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R(l13 (-305 -705) (250 250))
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R(l13 (-250 150) (250 250))
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R(l13 (1175 -225) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l14 (-3400 -350) (3000 900))
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R(l14 (-200 -900) (1000 900))
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R(l6 (-2175 -925) (775 950))
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)
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N(2
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R(l3 (-1500 1800) (3000 2000))
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R(l3 (-200 -2000) (1000 2000))
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R(l8 (-2010 -1310) (220 220))
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R(l8 (-220 180) (220 220))
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R(l8 (1190 -210) (200 200))
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R(l8 (-200 -600) (200 200))
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R(l12 (-1680 -280) (360 760))
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R(l12 (820 -830) (800 900))
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R(l13 (-1925 -775) (250 250))
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R(l13 (-250 150) (250 250))
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R(l13 (1175 -225) (200 200))
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R(l13 (-200 -600) (200 200))
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R(l14 (-3400 -350) (3000 900))
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R(l14 (-200 -900) (1000 900))
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R(l10 (-700 -950) (400 1000))
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R(l2 (-1875 -975) (775 950))
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)
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N(3
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R(l4 (-125 -250) (250 2500))
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R(l4 (-250 -3050) (250 1600))
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R(l4 (-250 1200) (250 1600))
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)
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N(4
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R(l8 (-510 -310) (220 220))
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R(l8 (-220 180) (220 220))
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R(l8 (-220 2180) (220 220))
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R(l8 (-220 180) (220 220))
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R(l12 (-290 -3530) (360 2840))
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R(l12 (-360 -2800) (360 760))
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R(l12 (-360 2040) (360 760))
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R(l2 (-680 -855) (775 950))
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R(l6 (-775 -3750) (775 950))
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)
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P(1 I(SUBSTRATE))
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P(2)
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P(3)
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P(4)
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D(1 D$PMOS
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Y(0 2800)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 4)
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T(G 3)
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T(D 2)
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T(B 2)
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)
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D(2 D$NMOS
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Y(0 0)
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E(L 0.25)
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E(W 0.95)
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E(AS 0.73625)
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E(AD 0.73625)
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E(PS 3.45)
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E(PD 3.45)
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T(S 4)
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T(G 3)
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T(D 1)
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T(B 1)
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)
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)
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X(TOP
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R((1500 800) (9080 4600))
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N(1
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R(l4 (2920 2600) (3980 400))
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R(l11 (-300 -300) (200 200))
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R(l12 (-300 -300) (690 400))
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)
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N(2 I(A)
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R(l4 (7700 2600) (2880 400))
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R(l15 (-2380 -200) (0 0))
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)
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N(3 I(Q)
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R(l12 (1810 2600) (690 400))
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R(l16 (-400 -200) (0 0))
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)
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N(4 I(VDD)
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R(l3 (4000 3400) (2700 2000))
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R(l17 (-2500 -1000) (0 0))
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)
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N(5 I('SUBSTRATE,VSS')
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R(l17 (4200 1500) (0 0))
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)
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P(2 I(A))
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P(3 I(Q))
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P(4 I(VDD))
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P(5 I('SUBSTRATE,VSS'))
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X(1 INV Y(3000 1600)
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P(0 5)
|
||||
P(1 4)
|
||||
P(2 1)
|
||||
P(3 3)
|
||||
)
|
||||
X(2 INV Y(7700 1600)
|
||||
P(0 5)
|
||||
P(1 4)
|
||||
P(2 2)
|
||||
P(3 1)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
# for debugging: _make_soft_connection_diodes(true)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,13 @@
|
|||
* Extracted by KLayout
|
||||
|
||||
.SUBCKT TOP A Q VDD SUBSTRATE|VSS
|
||||
X$1 Q SUBSTRATE|VSS VDD \$1 INV
|
||||
X$2 \$1 SUBSTRATE|VSS VDD A INV
|
||||
.ENDS TOP
|
||||
|
||||
.SUBCKT INV \$1 SUBSTRATE \$4 \$6
|
||||
M$1 \$4 \$6 \$1 \$4 PMOS L=0.25U W=0.95U AS=1.02125P AD=0.73625P PS=4.05U
|
||||
+ PD=3.45U
|
||||
M$2 SUBSTRATE \$6 \$1 SUBSTRATE NMOS L=0.25U W=0.95U AS=0.73625P AD=0.73625P
|
||||
+ PS=3.45U PD=3.45U
|
||||
.ENDS INV
|
||||
Binary file not shown.
|
|
@ -0,0 +1,201 @@
|
|||
#%l2n-klayout
|
||||
W(TOP)
|
||||
U(0.001)
|
||||
L(l3 '1/0')
|
||||
L(l4 '3/0')
|
||||
L(l15 '3/1')
|
||||
L(l8 '4/0')
|
||||
L(l11 '5/0')
|
||||
L(l12 '6/0')
|
||||
L(l16 '6/1')
|
||||
L(l13 '7/0')
|
||||
L(l14 '8/0')
|
||||
L(l17 '8/1')
|
||||
L(l7)
|
||||
L(l10)
|
||||
L(l2)
|
||||
L(l9)
|
||||
L(l6)
|
||||
C(l3 l3 l10)
|
||||
C(l4 l4 l15 l11)
|
||||
C(l15 l4 l15)
|
||||
C(l8 l8 l12 l10 l2 l9 l6)
|
||||
CS(l8 l10 l2 l9 l6)
|
||||
C(l11 l4 l11 l12)
|
||||
CS(l11 l4)
|
||||
C(l12 l8 l11 l12 l16 l13)
|
||||
C(l16 l12 l16)
|
||||
C(l13 l12 l13 l14)
|
||||
C(l14 l13 l14 l17)
|
||||
C(l17 l14 l17)
|
||||
C(l7 l7)
|
||||
C(l10 l3 l8 l10)
|
||||
CS(l10 l3)
|
||||
C(l2 l8 l2)
|
||||
C(l9 l8 l9)
|
||||
C(l6 l8 l6)
|
||||
G(l7 SUBSTRATE)
|
||||
G(l9 SUBSTRATE)
|
||||
GS(l9 SUBSTRATE)
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - $2') C(TOP) Q('(6.54,2.6;6.54,4.78;6.9,4.78;6.9,2.6)'))
|
||||
H(B('\tPartial net #2: TOP - $I3') C(TOP) Q('(7.12,1.18;7.12,4.78;7.48,4.78;7.48,1.18)'))
|
||||
H(W B('Net with incomplete wiring (soft-connected partial nets)') C(TOP) X('soft-connection-check'))
|
||||
H(B('\tPartial net #1: TOP - Q') C(TOP) Q('(1.81,1.18;1.81,4.78;2.78,4.78;2.78,1.18)'))
|
||||
H(B('\tPartial net #2: TOP - $I2') C(TOP) Q('(1.84,4.02;1.84,4.78;2.2,4.78;2.2,4.02)'))
|
||||
K(PMOS MOS4)
|
||||
K(NMOS MOS4)
|
||||
D(D$PMOS PMOS
|
||||
T(S
|
||||
R(l2 (-1200 -475) (1075 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l2 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l3 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
D(D$NMOS NMOS
|
||||
T(S
|
||||
R(l6 (-900 -475) (775 950))
|
||||
)
|
||||
T(G
|
||||
R(l4 (-125 -475) (250 950))
|
||||
)
|
||||
T(D
|
||||
R(l6 (125 -475) (775 950))
|
||||
)
|
||||
T(B
|
||||
R(l7 (-125 -475) (250 950))
|
||||
)
|
||||
)
|
||||
X(INV
|
||||
R((-1500 -800) (3800 4600))
|
||||
N(1
|
||||
R(l8 (-1090 2490) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (360 -3420) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (-220 2180) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (-870 -690) (360 760))
|
||||
R(l12 (220 -3600) (360 2840))
|
||||
R(l12 (-360 -2800) (360 760))
|
||||
R(l12 (-360 2040) (360 760))
|
||||
R(l2 (-980 -855) (1075 950))
|
||||
R(l6 (-775 -3750) (775 950))
|
||||
)
|
||||
N(2 I(SUBSTRATE)
|
||||
R(l8 (1700 100) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l8 (-1610 -210) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l12 (890 -760) (800 900))
|
||||
R(l12 (-1980 -830) (360 760))
|
||||
R(l13 (-305 -705) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l6 (-2175 -925) (775 950))
|
||||
)
|
||||
N(3
|
||||
R(l3 (-1500 1800) (3000 2000))
|
||||
R(l3 (-200 -2000) (1000 2000))
|
||||
R(l8 (-2010 -1310) (220 220))
|
||||
R(l8 (-220 180) (220 220))
|
||||
R(l8 (1190 -210) (200 200))
|
||||
R(l8 (-200 -600) (200 200))
|
||||
R(l12 (-1680 -280) (360 760))
|
||||
R(l12 (820 -830) (800 900))
|
||||
R(l13 (-1925 -775) (250 250))
|
||||
R(l13 (-250 150) (250 250))
|
||||
R(l13 (1175 -225) (200 200))
|
||||
R(l13 (-200 -600) (200 200))
|
||||
R(l14 (-3400 -350) (3000 900))
|
||||
R(l14 (-200 -900) (1000 900))
|
||||
R(l10 (-700 -950) (400 1000))
|
||||
R(l2 (-1875 -975) (775 950))
|
||||
)
|
||||
N(4
|
||||
R(l4 (-125 -250) (250 2500))
|
||||
R(l4 (-250 -3050) (250 1600))
|
||||
R(l4 (-250 1200) (250 1600))
|
||||
)
|
||||
P(1)
|
||||
P(2 I(SUBSTRATE))
|
||||
P(3)
|
||||
P(4)
|
||||
D(1 D$PMOS
|
||||
Y(0 2800)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 1.02125)
|
||||
E(AD 0.73625)
|
||||
E(PS 4.05)
|
||||
E(PD 3.45)
|
||||
T(S 1)
|
||||
T(G 4)
|
||||
T(D 3)
|
||||
T(B 3)
|
||||
)
|
||||
D(2 D$NMOS
|
||||
Y(0 0)
|
||||
E(L 0.25)
|
||||
E(W 0.95)
|
||||
E(AS 0.73625)
|
||||
E(AD 0.73625)
|
||||
E(PS 3.45)
|
||||
E(PD 3.45)
|
||||
T(S 1)
|
||||
T(G 4)
|
||||
T(D 2)
|
||||
T(B 2)
|
||||
)
|
||||
)
|
||||
X(TOP
|
||||
R((1500 800) (9080 4600))
|
||||
N(1
|
||||
R(l4 (2920 2600) (3980 400))
|
||||
R(l11 (-300 -300) (200 200))
|
||||
R(l12 (-260 -300) (360 1600))
|
||||
)
|
||||
N(2 I(A)
|
||||
R(l4 (7700 2600) (2880 400))
|
||||
R(l15 (-2380 -200) (0 0))
|
||||
)
|
||||
N(3 I(Q)
|
||||
R(l12 (1810 2600) (690 400))
|
||||
R(l16 (-400 -200) (0 0))
|
||||
)
|
||||
N(4 I(VDD)
|
||||
R(l3 (4000 3400) (2700 2000))
|
||||
R(l14 (-1500 -1450) (1200 900))
|
||||
R(l17 (-2200 -450) (0 0))
|
||||
)
|
||||
N(5 I('SUBSTRATE,VSS')
|
||||
R(l14 (5200 1150) (1200 900))
|
||||
R(l17 (-2200 -550) (0 0))
|
||||
)
|
||||
P(2 I(A))
|
||||
P(3 I(Q))
|
||||
P(4 I(VDD))
|
||||
P(5 I('SUBSTRATE,VSS'))
|
||||
X(1 INV Y(3000 1600)
|
||||
P(0 3)
|
||||
P(1 5)
|
||||
P(2 4)
|
||||
P(3 1)
|
||||
)
|
||||
X(2 INV Y(7700 1600)
|
||||
P(0 1)
|
||||
P(1 5)
|
||||
P(2 4)
|
||||
P(3 2)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,93 @@
|
|||
|
||||
$lvs_test_source && source($lvs_test_source)
|
||||
|
||||
if $lvs_test_target_l2n
|
||||
report_netlist($lvs_test_target_l2n)
|
||||
else
|
||||
report_netlist
|
||||
end
|
||||
|
||||
writer = write_spice(true, false)
|
||||
$lvs_test_target_cir && target_netlist($lvs_test_target_cir, writer, "Extracted by KLayout")
|
||||
|
||||
deep
|
||||
|
||||
# Drawing layers
|
||||
|
||||
nwell = input(1, 0)
|
||||
active = input(2, 0)
|
||||
nplus = input(2, 1)
|
||||
pplus = input(2, 2)
|
||||
poly = input(3, 0)
|
||||
poly_lbl = input(3, 1)
|
||||
diff_cont = input(4, 0)
|
||||
poly_cont = input(5, 0)
|
||||
metal1 = input(6, 0)
|
||||
metal1_lbl = input(6, 1)
|
||||
via1 = input(7, 0)
|
||||
metal2 = input(8, 0)
|
||||
metal2_lbl = input(8, 1)
|
||||
|
||||
# Bulk layer for terminal provisioning
|
||||
|
||||
bulk = polygon_layer
|
||||
|
||||
psd = nil
|
||||
nsd = nil
|
||||
|
||||
# Computed layers
|
||||
|
||||
active_in_nwell = active & nwell
|
||||
pactive = active_in_nwell & pplus
|
||||
ntie = active_in_nwell & nplus
|
||||
pgate = pactive & poly
|
||||
psd = pactive - pgate
|
||||
|
||||
active_outside_nwell = active - nwell
|
||||
nactive = active_outside_nwell & nplus
|
||||
ptie = active_outside_nwell & pplus
|
||||
ngate = nactive & poly
|
||||
nsd = nactive - ngate
|
||||
|
||||
# Device extraction
|
||||
|
||||
# PMOS transistor device extraction
|
||||
extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
|
||||
"tS" => psd, "tD" => psd, "tG" => poly })
|
||||
|
||||
# NMOS transistor device extraction
|
||||
extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
|
||||
"tS" => nsd, "tD" => nsd, "tG" => poly })
|
||||
|
||||
# Define connectivity for netlist extraction
|
||||
|
||||
# Inter-layer
|
||||
|
||||
soft_connect(diff_cont, psd)
|
||||
soft_connect(diff_cont, nsd)
|
||||
soft_connect(diff_cont, ptie)
|
||||
soft_connect(diff_cont, ntie)
|
||||
soft_connect(ntie, nwell)
|
||||
soft_connect(poly_cont, poly)
|
||||
|
||||
connect(diff_cont, metal1)
|
||||
connect(poly_cont, metal1)
|
||||
connect(metal1, via1)
|
||||
connect(via1, metal2)
|
||||
|
||||
# attach labels
|
||||
connect(poly, poly_lbl)
|
||||
connect(metal1, metal1_lbl)
|
||||
connect(metal2, metal2_lbl)
|
||||
|
||||
# Global
|
||||
connect_global(bulk, "SUBSTRATE")
|
||||
soft_connect_global(ptie, "SUBSTRATE")
|
||||
|
||||
# Netlist section (NOTE: we only check log here)
|
||||
# for debugging: _make_soft_connection_diodes(true)
|
||||
netlist
|
||||
|
||||
netlist.simplify
|
||||
|
||||
|
||||
Loading…
Reference in New Issue