mirror of
https://github.com/KLayout/klayout.git
synced 2026-09-08 04:08:14 +02:00
Added the new feature: 'flag_missing_ports'
This commit is contained in:
Matthias Koefferlein
Vendored
+23
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* Extracted by KLayout
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* cell ND2X1
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* pin VSS
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* pin VDD
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* pin b
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* pin X
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* pin SUBSTRATE
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.SUBCKT ND2X1 1 3 5 6 7
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* net 1 VSS
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* net 3 VDD
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* net 5 b
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* net 6 X
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* net 7 SUBSTRATE
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* device instance $1 r0 *1 0.85,5.8 PMOS
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M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
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* device instance $2 r0 *1 1.55,5.8 PMOS
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M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
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* device instance $3 r0 *1 0.85,2.135 NMOS
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M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
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* device instance $4 r0 *1 1.55,2.135 NMOS
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M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
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.ENDS ND2X1
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Vendored
BIN
Binary file not shown.
Vendored
+76
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source($lvs_test_source, "ND2X1")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("flag_missing_ports.sch")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.simplify
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compare
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flag_missing_ports
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+362
@@ -0,0 +1,362 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(ND2X1)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12)
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layer(l13)
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layer(l7)
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l7 l7)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l2 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (450 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(l2 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l6 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (450 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$1 NMOS
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terminal(S
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rect(l6 (-575 -475) (450 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Circuit boundary
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rect((-100 400) (2600 7600))
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# Nets with their geometries
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net(1 name(VSS)
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rect(l8 (1110 5160) (180 180))
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rect(l8 (-180 920) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l11 (-240 -790) (300 1700))
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rect(l11 (-1350 0) (2400 800))
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rect(l11 (-1150 -400) (0 0))
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rect(l2 (-275 -2150) (425 1500))
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rect(l2 (-400 -1500) (425 1500))
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)
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net(2
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rect(l8 (1810 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-1580 3760) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (1220 920) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
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rect(l11 (-110 1390) (300 1400))
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polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
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rect(l11 (-1890 600) (300 1400))
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rect(l11 (1100 -1700) (300 300))
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rect(l11 (-300 0) (300 1400))
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rect(l2 (-1750 -1450) (425 1500))
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rect(l2 (950 -1500) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(3 name(VDD)
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rect(l8 (410 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -1300) (300 1360))
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rect(l11 (-650 -2160) (2400 800))
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rect(l11 (-1150 -400) (0 0))
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rect(l6 (-950 860) (425 950))
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)
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net(4
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rect(l3 (-100 4500) (2600 3500))
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)
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net(5 name(b)
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rect(l4 (1425 2860) (250 1940))
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rect(l4 (-345 -950) (300 300))
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rect(l4 (-205 650) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-285 1050) (180 180))
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rect(l11 (-70 -90) (0 0))
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rect(l11 (-170 -150) (300 300))
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)
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net(6 name(X)
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rect(l4 (725 2860) (250 1940))
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rect(l4 (-325 -1850) (300 300))
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rect(l4 (-225 1550) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-265 150) (180 180))
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rect(l11 (-90 -90) (0 0))
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rect(l11 (-150 -150) (300 300))
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)
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net(7 name(SUBSTRATE))
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net(8
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rect(l6 (975 1660) (425 950))
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rect(l6 (-400 -950) (425 950))
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)
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# Outgoing pins and their connections to nets
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pin(1 name(VSS))
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pin(3 name(VDD))
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pin(5 name(b))
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pin(6 name(X))
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pin(7 name(SUBSTRATE))
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# Devices and their connections
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device(1 D$PMOS
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location(850 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.6375)
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param(AD 0.3375)
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param(PS 3.85)
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param(PD 1.95)
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terminal(S 2)
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terminal(G 6)
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terminal(D 1)
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terminal(B 4)
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)
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device(2 D$PMOS$1
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location(1550 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.3375)
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param(AD 0.6375)
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param(PS 1.95)
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param(PD 3.85)
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terminal(S 1)
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terminal(G 5)
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terminal(D 2)
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terminal(B 4)
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)
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device(3 D$NMOS
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location(850 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.40375)
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param(AD 0.21375)
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param(PS 2.75)
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param(PD 1.4)
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terminal(S 3)
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terminal(G 6)
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terminal(D 8)
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terminal(B 7)
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)
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device(4 D$NMOS$1
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location(1550 2135)
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param(L 0.25)
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param(W 0.95)
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param(AS 0.21375)
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param(AD 0.40375)
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param(PS 1.4)
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param(PD 2.75)
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terminal(S 8)
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terminal(G 5)
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terminal(D 2)
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terminal(B 7)
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)
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)
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)
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# Reference netlist
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reference(
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Nets
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net(1 name(VDD))
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net(2 name(OUT))
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net(3 name(VSS))
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net(4 name(NWELL))
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net(5 name(B))
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net(6 name(A))
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net(7 name(BULK))
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net(8 name('1'))
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# Outgoing pins and their connections to nets
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pin(1 name(VDD))
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pin(2 name(OUT))
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pin(3 name(VSS))
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pin(4 name(NWELL))
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pin(5 name(B))
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pin(6 name(A))
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pin(7 name(BULK))
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# Devices and their connections
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device(1 PMOS
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name($1)
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param(L 0.25)
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param(W 1.5)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 1)
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terminal(G 6)
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terminal(D 2)
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terminal(B 4)
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)
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device(2 PMOS
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name($2)
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param(L 0.25)
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param(W 1.5)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 1)
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terminal(G 5)
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terminal(D 2)
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terminal(B 4)
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)
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device(3 NMOS
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name($3)
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param(L 0.25)
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param(W 0.95)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 3)
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terminal(G 6)
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terminal(D 8)
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terminal(B 7)
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)
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device(4 NMOS
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name($4)
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param(L 0.25)
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param(W 0.95)
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param(AS 0)
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param(AD 0)
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param(PS 0)
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param(PD 0)
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terminal(S 8)
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terminal(G 5)
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terminal(D 2)
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terminal(B 7)
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)
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)
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)
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# Cross reference
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xref(
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circuit(ND2X1 ND2X1 match
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log(
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entry(error description('Port mismatch \'$4\' vs. \'NWELL\''))
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entry(error description('Port mismatch \'$2\' vs. \'OUT\''))
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entry(error description('Port mismatch \'SUBSTRATE\' vs. \'BULK\''))
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entry(error description('Port mismatch \'VDD\' vs. \'VSS\''))
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entry(error description('Port mismatch \'VSS\' vs. \'VDD\''))
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entry(error description('Port mismatch \'X\' vs. \'A\''))
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)
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xref(
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net(8 8 match)
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net(4 4 match)
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net(2 2 match)
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net(7 7 match)
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net(3 3 match)
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net(1 1 match)
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net(6 6 match)
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net(5 5 match)
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pin(() 3 match)
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pin(() 1 match)
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pin(4 6 match)
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pin(1 2 match)
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pin(0 0 match)
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pin(3 5 match)
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pin(2 4 match)
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device(3 3 match)
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device(4 4 match)
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device(1 1 match)
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device(2 2 match)
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)
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)
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)
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Vendored
+7
@@ -0,0 +1,7 @@
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.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK
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M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U
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M$2 OUT B VDD NWELL PMOS L=0.25U W=1.5U
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M$3 1 A VSS BULK NMOS L=0.25U W=0.95U
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M$4 OUT B 1 BULK NMOS L=0.25U W=0.95U
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.ENDS ND2X1
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Reference in New Issue
Block a user