mirror of https://github.com/KLayout/klayout.git
Added the new feature: 'flag_missing_ports'
This commit is contained in:
Matthias Koefferlein
parent
7b865451ee
commit
094e11897a
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@ -25,6 +25,7 @@
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#include "dbLayoutVsSchematic.h"
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#include "dbLayoutVsSchematicWriter.h"
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#include "dbLayoutVsSchematicReader.h"
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#include "dbNetlistCompareUtils.h"
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namespace db
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{
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@ -86,6 +87,43 @@ db::NetlistCrossReference *LayoutVsSchematic::make_cross_ref ()
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return mp_cross_ref.get ();
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}
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bool
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LayoutVsSchematic::flag_missing_ports (const db::Circuit *circuit)
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{
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if (! mp_cross_ref.get ()) {
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return false;
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}
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db::NetlistCrossReference::PerCircuitData *pcd = const_cast<db::NetlistCrossReference::PerCircuitData *> (mp_cross_ref->per_circuit_data_for (std::make_pair (circuit, circuit)));
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if (! pcd) {
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return false;
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}
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bool error = false;
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for (auto n = pcd->nets.begin (); n != pcd->nets.end (); ++n) {
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const db::Net *schem = n->pair.second;
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const db::Net *layout = n->pair.first;
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if (schem && layout && schem->begin_pins () != schem->end_pins ()) {
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if (db::name_compare (layout, schem) != 0) {
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std::string msg = tl::sprintf (tl::to_string (tr ("Port mismatch '%s' vs. '%s'")), layout->expanded_name (), schem->expanded_name ());
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db::LogEntryData entry (db::Error, msg);
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pcd->log_entries.push_back (entry);
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error = true;
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}
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}
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}
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return !error;
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}
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void LayoutVsSchematic::save (const std::string &path, bool short_format)
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{
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@ -144,6 +144,22 @@ public:
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*/
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db::NetlistCrossReference *make_cross_ref ();
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/**
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* @brief Checks top-level port names
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*
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* This method checks that every top-level pin has a corresponding
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* schematic pin and their names are equivalent. This verifies that
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* all pins are labelles properly.
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*
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* Errors are placed in the log file. The return values indicates
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* if there are no errors.
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*
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* The circuit is either a schematic or layout circuit.
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*
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* See issue #2055.
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*/
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bool flag_missing_ports (const db::Circuit *circuit);
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/**
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* @brief Saves the database to the given path
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*
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@ -110,6 +110,18 @@ Class<db::LayoutVsSchematic> decl_dbLayoutVsSchematic (decl_dbLayoutToNetlist, "
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"\n"
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"See \\NetlistCrossReference for more details.\n"
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) +
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gsi::method ("flag_missing_ports", &db::LayoutVsSchematic::flag_missing_ports, gsi::arg ("circuit"),
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"@brief Flags inconsistent port labels in the given circuit\n"
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"@param circuit Either a layout or schematic circuit\n"
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"@return True, if no errors were found\n"
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"This method will check all schematic nets which have pins and tests whether the corresponding layout net "
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"has the same name. This way, it is checked if the pins are properly labelled.\n"
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"\n"
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"The method must be called after the compare step was successful. Error messages will be added "
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"to the log entries. If an error occured or the cross reference is not value, 'false' is returned.\n"
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"\n"
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"This method was introduced in version 0.30.2."
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) +
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gsi::method_ext ("write_l2n", &save_l2n, gsi::arg ("path"), gsi::arg ("short_format", false),
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"@brief Writes the \\LayoutToNetlist part of the object to a file.\n"
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"This method employs the native format of KLayout.\n"
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@ -225,9 +225,16 @@ module LVS
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# @synopsis lvs_data
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# See \Netter#lvs_data for a description of that function.
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# %LVS%
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# @name flag_missing_ports
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# @brief Checks if all top level ports are properly labelled
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# @synopsis flag_missing_ports
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# See \Netter#flag_missing_ports for a description of that function.
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%w(schematic compare split_gates join_symmetric_nets tolerance ignore_parameter enable_parameter disable_parameter
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blank_circuit align same_nets same_nets! same_circuits same_device_classes equivalent_pins
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min_caps max_res max_depth max_branch_complexity consider_net_names lvs_data no_lvs_hints).each do |f|
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min_caps max_res max_depth max_branch_complexity consider_net_names lvs_data no_lvs_hints
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flag_missing_ports).each do |f|
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eval <<"CODE"
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def #{f}(*args)
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_netter.#{f}(*args)
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@ -530,6 +530,33 @@ CODE
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@comparer_config << lambda { |comparer| comparer.with_log = false }
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end
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# %LVS%
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# @name flag_missing_ports
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# @brief Flags inconsistently labelled or missing ports in the current top circuit
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# @synopsis flag_missing_ports
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# This method must be called after "compare" was executed successfully and will
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# report errors if pins in the current top circuit's schematic are not labelled
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# correspondingly in the layout. This prevents swapping of port labels or
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# pads.
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#
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# @code
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# success = compare
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# success && flag_missing_ports
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# @/code
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#
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# Note that in order to use this method, the top circuit from the schematic netlist
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# needs to have pins. This may not be always the case - for example, if the top
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# level circuit is not a subcircuit in a Spice netlist.
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def flag_missing_ports
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lvs_data.netlist || raise("Netlist not extracted yet")
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lvs_data.xref || raise("Compare step was not executed yet")
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lvs_data.flag_missing_ports(lvs_data.netlist.top_circuit)
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end
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# %LVS%
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# @name same_nets
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# @brief Establishes an equivalence between the nets
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@ -357,3 +357,8 @@ TEST(62_LayerNames)
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run_test (_this, "layer_names", "layer_names.gds", false, true, "TOP");
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}
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TEST(63_FlagMissingPorts)
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{
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run_test (_this, "flag_missing_ports", "flag_missing_ports.gds", false, true, "TOP");
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}
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@ -0,0 +1,23 @@
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* Extracted by KLayout
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* cell ND2X1
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* pin VSS
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* pin VDD
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* pin b
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* pin X
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* pin SUBSTRATE
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.SUBCKT ND2X1 1 3 5 6 7
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* net 1 VSS
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* net 3 VDD
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* net 5 b
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* net 6 X
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* net 7 SUBSTRATE
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* device instance $1 r0 *1 0.85,5.8 PMOS
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M$1 1 6 2 4 PMOS L=0.25U W=1.5U AS=0.6375P AD=0.3375P PS=3.85U PD=1.95U
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* device instance $2 r0 *1 1.55,5.8 PMOS
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M$2 2 5 1 4 PMOS L=0.25U W=1.5U AS=0.3375P AD=0.6375P PS=1.95U PD=3.85U
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* device instance $3 r0 *1 0.85,2.135 NMOS
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M$3 8 6 3 7 NMOS L=0.25U W=0.95U AS=0.40375P AD=0.21375P PS=2.75U PD=1.4U
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* device instance $4 r0 *1 1.55,2.135 NMOS
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M$4 2 5 8 7 NMOS L=0.25U W=0.95U AS=0.21375P AD=0.40375P PS=1.4U PD=2.75U
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.ENDS ND2X1
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Binary file not shown.
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@ -0,0 +1,76 @@
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source($lvs_test_source, "ND2X1")
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report_lvs($lvs_test_target_lvsdb, true)
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target_netlist($lvs_test_target_cir, write_spice, "Extracted by KLayout")
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schematic("flag_missing_ports.sch")
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deep
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(8, 0)
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metal1 = input(9, 0)
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via1 = input(10, 0)
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metal2 = input(11, 0)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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ntie = active_in_nwell & nplus
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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ptie = active_outside_nwell & pplus
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(ntie, contact)
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connect(nwell, ntie)
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connect(ptie, contact)
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connect(contact, metal1)
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connect(metal1, via1)
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connect(via1, metal2)
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(ptie, "SUBSTRATE")
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# Compare section
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netlist.simplify
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compare
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flag_missing_ports
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@ -0,0 +1,362 @@
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#%lvsdb-klayout
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# Layout
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layout(
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top(ND2X1)
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unit(0.001)
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# Layer section
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# This section lists the mask layers (drawing or derived) and their connections.
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# Mask layers
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layer(l3 '1/0')
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layer(l4 '5/0')
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layer(l8 '8/0')
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layer(l11 '9/0')
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layer(l12)
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layer(l13)
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layer(l7)
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layer(l2)
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layer(l9)
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layer(l6)
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layer(l10)
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# Mask layer connectivity
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connect(l3 l3 l9)
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connect(l4 l4 l8)
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connect(l8 l4 l8 l11 l2 l9 l6 l10)
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connect(l11 l8 l11 l12)
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connect(l12 l11 l12 l13)
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connect(l13 l12 l13)
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connect(l7 l7)
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connect(l2 l8 l2)
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connect(l9 l3 l8 l9)
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connect(l6 l8 l6)
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connect(l10 l8 l10)
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# Global nets and connectivity
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global(l7 SUBSTRATE)
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global(l10 SUBSTRATE)
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# Device class section
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class(PMOS MOS4)
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class(NMOS MOS4)
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# Device abstracts section
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# Device abstracts list the pin shapes of the devices.
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device(D$PMOS PMOS
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terminal(S
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rect(l2 (-550 -750) (425 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (450 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$PMOS$1 PMOS
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terminal(S
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rect(l2 (-575 -750) (450 1500))
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)
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terminal(G
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rect(l4 (-125 -750) (250 1500))
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)
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terminal(D
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rect(l2 (125 -750) (425 1500))
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)
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terminal(B
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rect(l3 (-125 -750) (250 1500))
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)
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)
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device(D$NMOS NMOS
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terminal(S
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rect(l6 (-550 -475) (425 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (450 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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device(D$NMOS$1 NMOS
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terminal(S
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rect(l6 (-575 -475) (450 950))
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)
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terminal(G
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rect(l4 (-125 -475) (250 950))
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)
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terminal(D
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rect(l6 (125 -475) (425 950))
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)
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terminal(B
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rect(l7 (-125 -475) (250 950))
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)
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)
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# Circuit section
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# Circuits are the hierarchical building blocks of the netlist.
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circuit(ND2X1
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# Circuit boundary
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rect((-100 400) (2600 7600))
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# Nets with their geometries
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net(1 name(VSS)
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rect(l8 (1110 5160) (180 180))
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rect(l8 (-180 920) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l11 (-240 -790) (300 1700))
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rect(l11 (-1350 0) (2400 800))
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rect(l11 (-1150 -400) (0 0))
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rect(l2 (-275 -2150) (425 1500))
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rect(l2 (-400 -1500) (425 1500))
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)
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net(2
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rect(l8 (1810 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l8 (-1580 3760) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (-180 -730) (180 180))
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rect(l8 (1220 920) (180 180))
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rect(l8 (-180 -1280) (180 180))
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rect(l8 (-180 370) (180 180))
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polygon(l11 (-240 -4180) (0 1390) (490 0) (0 -300) (-190 0) (0 -1090))
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rect(l11 (-110 1390) (300 1400))
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polygon(l11 (-1890 0) (0 600) (300 0) (0 -300) (1590 0) (0 -300))
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rect(l11 (-1890 600) (300 1400))
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rect(l11 (1100 -1700) (300 300))
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rect(l11 (-300 0) (300 1400))
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rect(l2 (-1750 -1450) (425 1500))
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rect(l2 (950 -1500) (425 1500))
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rect(l6 (-425 -4890) (425 950))
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)
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net(3 name(VDD)
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rect(l8 (410 1770) (180 180))
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rect(l8 (-180 370) (180 180))
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rect(l11 (-240 -1300) (300 1360))
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rect(l11 (-650 -2160) (2400 800))
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rect(l11 (-1150 -400) (0 0))
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rect(l6 (-950 860) (425 950))
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)
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net(4
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rect(l3 (-100 4500) (2600 3500))
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)
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net(5 name(b)
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rect(l4 (1425 2860) (250 1940))
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rect(l4 (-345 -950) (300 300))
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rect(l4 (-205 650) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-285 1050) (180 180))
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rect(l11 (-70 -90) (0 0))
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rect(l11 (-170 -150) (300 300))
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)
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net(6 name(X)
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rect(l4 (725 2860) (250 1940))
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rect(l4 (-325 -1850) (300 300))
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rect(l4 (-225 1550) (250 2000))
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rect(l4 (-250 -2000) (250 2000))
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rect(l4 (-250 -5390) (250 1450))
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rect(l8 (-265 150) (180 180))
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rect(l11 (-90 -90) (0 0))
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rect(l11 (-150 -150) (300 300))
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)
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net(7 name(SUBSTRATE))
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net(8
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rect(l6 (975 1660) (425 950))
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rect(l6 (-400 -950) (425 950))
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)
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# Outgoing pins and their connections to nets
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pin(1 name(VSS))
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pin(3 name(VDD))
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pin(5 name(b))
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pin(6 name(X))
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pin(7 name(SUBSTRATE))
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# Devices and their connections
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device(1 D$PMOS
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location(850 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.6375)
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param(AD 0.3375)
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param(PS 3.85)
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param(PD 1.95)
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terminal(S 2)
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terminal(G 6)
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terminal(D 1)
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terminal(B 4)
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)
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device(2 D$PMOS$1
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location(1550 5800)
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param(L 0.25)
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param(W 1.5)
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param(AS 0.3375)
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param(AD 0.6375)
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||||
param(PS 1.95)
|
||||
param(PD 3.85)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 D$NMOS
|
||||
location(850 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.40375)
|
||||
param(AD 0.21375)
|
||||
param(PS 2.75)
|
||||
param(PD 1.4)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 D$NMOS$1
|
||||
location(1550 2135)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0.21375)
|
||||
param(AD 0.40375)
|
||||
param(PS 1.4)
|
||||
param(PD 2.75)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Reference netlist
|
||||
reference(
|
||||
|
||||
# Device class section
|
||||
class(PMOS MOS4)
|
||||
class(NMOS MOS4)
|
||||
|
||||
# Circuit section
|
||||
# Circuits are the hierarchical building blocks of the netlist.
|
||||
circuit(ND2X1
|
||||
|
||||
# Nets
|
||||
net(1 name(VDD))
|
||||
net(2 name(OUT))
|
||||
net(3 name(VSS))
|
||||
net(4 name(NWELL))
|
||||
net(5 name(B))
|
||||
net(6 name(A))
|
||||
net(7 name(BULK))
|
||||
net(8 name('1'))
|
||||
|
||||
# Outgoing pins and their connections to nets
|
||||
pin(1 name(VDD))
|
||||
pin(2 name(OUT))
|
||||
pin(3 name(VSS))
|
||||
pin(4 name(NWELL))
|
||||
pin(5 name(B))
|
||||
pin(6 name(A))
|
||||
pin(7 name(BULK))
|
||||
|
||||
# Devices and their connections
|
||||
device(1 PMOS
|
||||
name($1)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 6)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(2 PMOS
|
||||
name($2)
|
||||
param(L 0.25)
|
||||
param(W 1.5)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 1)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 4)
|
||||
)
|
||||
device(3 NMOS
|
||||
name($3)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 3)
|
||||
terminal(G 6)
|
||||
terminal(D 8)
|
||||
terminal(B 7)
|
||||
)
|
||||
device(4 NMOS
|
||||
name($4)
|
||||
param(L 0.25)
|
||||
param(W 0.95)
|
||||
param(AS 0)
|
||||
param(AD 0)
|
||||
param(PS 0)
|
||||
param(PD 0)
|
||||
terminal(S 8)
|
||||
terminal(G 5)
|
||||
terminal(D 2)
|
||||
terminal(B 7)
|
||||
)
|
||||
|
||||
)
|
||||
)
|
||||
|
||||
# Cross reference
|
||||
xref(
|
||||
circuit(ND2X1 ND2X1 match
|
||||
log(
|
||||
entry(error description('Port mismatch \'$4\' vs. \'NWELL\''))
|
||||
entry(error description('Port mismatch \'$2\' vs. \'OUT\''))
|
||||
entry(error description('Port mismatch \'SUBSTRATE\' vs. \'BULK\''))
|
||||
entry(error description('Port mismatch \'VDD\' vs. \'VSS\''))
|
||||
entry(error description('Port mismatch \'VSS\' vs. \'VDD\''))
|
||||
entry(error description('Port mismatch \'X\' vs. \'A\''))
|
||||
)
|
||||
xref(
|
||||
net(8 8 match)
|
||||
net(4 4 match)
|
||||
net(2 2 match)
|
||||
net(7 7 match)
|
||||
net(3 3 match)
|
||||
net(1 1 match)
|
||||
net(6 6 match)
|
||||
net(5 5 match)
|
||||
pin(() 3 match)
|
||||
pin(() 1 match)
|
||||
pin(4 6 match)
|
||||
pin(1 2 match)
|
||||
pin(0 0 match)
|
||||
pin(3 5 match)
|
||||
pin(2 4 match)
|
||||
device(3 3 match)
|
||||
device(4 4 match)
|
||||
device(1 1 match)
|
||||
device(2 2 match)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,7 @@
|
|||
|
||||
.SUBCKT ND2X1 VDD OUT VSS NWELL B A BULK
|
||||
M$1 OUT A VDD NWELL PMOS L=0.25U W=1.5U
|
||||
M$2 OUT B VDD NWELL PMOS L=0.25U W=1.5U
|
||||
M$3 1 A VSS BULK NMOS L=0.25U W=0.95U
|
||||
M$4 OUT B 1 BULK NMOS L=0.25U W=0.95U
|
||||
.ENDS ND2X1
|
||||
Loading…
Reference in New Issue