klayout/testdata/lvs/inv.lvsdb

#%lvsdb-klayout

# Layout
layout(
 top(INVERTER)
 unit(0.001)

 # Layer section
 # This section lists the mask layers (drawing or derived) and their connections.

 # Mask layers
 layer(l3 'NWELL (1/0)')
 layer(l4 'POLY (5/0)')
 layer(l8 'CONTACT (6/0)')
 layer(l9 'METAL1 (7/0)')
 layer(l10 'METAL1_LABEL (7/1)')
 layer(l11 'VIA1 (8/0)')
 layer(l12 'METAL2 (9/0)')
 layer(l13 'METAL2_LABEL (9/1)')
 layer(l7)
 layer(l2)
 layer(l6)

 # Mask layer connectivity
 connect(l3 l3)
 connect(l4 l4 l8)
 connect(l8 l4 l8 l9 l2 l6)
 connect(l9 l8 l9 l10 l11)
 connect(l10 l9)
 connect(l11 l9 l11 l12)
 connect(l12 l11 l12 l13)
 connect(l13 l12)
 connect(l7 l7)
 connect(l2 l8 l2)
 connect(l6 l8 l6)

 # Global nets and connectivity
 global(l3 NWELL)
 global(l7 SUBSTRATE)

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Device abstracts section
 # Device abstracts list the pin shapes of the devices.
 device(D$PMOS PMOS
  terminal(S
   rect(l2 (-575 -750) (450 1500))
  )
  terminal(G
   rect(l4 (-125 -750) (250 1500))
  )
  terminal(D
   rect(l2 (125 -750) (450 1500))
  )
  terminal(B
   rect(l3 (-125 -750) (250 1500))
  )
 )
 device(D$NMOS NMOS
  terminal(S
   rect(l6 (-575 -450) (450 900))
  )
  terminal(G
   rect(l4 (-125 -450) (250 900))
  )
  terminal(D
   rect(l6 (125 -450) (450 900))
  )
  terminal(B
   rect(l7 (-125 -450) (250 900))
  )
 )

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(INVERTER

  # Circuit boundary
  rect((0 0) (2000 6150))

  # Nets with their geometries
  net(1 name(IN)
   rect(l4 (900 50) (250 1050))
   rect(l4 (-250 0) (250 3100))
   rect(l4 (-250 0) (250 1650))
   rect(l4 (-800 -3100) (550 400))
   rect(l8 (-450 -300) (200 200))
   rect(l9 (-300 -300) (400 400))
   text(l10 IN (-200 -200))
  )
  net(2 name(VSS)
   rect(l8 (550 300) (200 200))
   rect(l8 (-200 300) (200 200))
   rect(l9 (-250 -950) (300 1050))
   rect(l11 (-250 -950) (200 200))
   rect(l11 (-200 300) (200 200))
   rect(l12 (-750 -850) (2000 1000))
   text(l13 VSS (-100 -850))
   rect(l6 (-1450 50) (450 900))
  )
  net(3 name(VDD)
   rect(l8 (550 4350) (200 200))
   rect(l8 (-200 300) (200 200))
   rect(l8 (-200 300) (200 200))
   rect(l9 (-250 -1300) (300 1600))
   rect(l11 (-250 -800) (200 200))
   rect(l11 (-200 300) (200 200))
   rect(l12 (-750 -850) (2000 1000))
   text(l13 VDD (-150 -850))
   rect(l2 (-1400 -850) (450 1500))
  )
  net(4 name(OUT)
   rect(l8 (1300 4350) (200 200))
   rect(l8 (-200 300) (200 200))
   rect(l8 (-200 300) (200 200))
   rect(l8 (-200 -5250) (200 200))
   rect(l8 (-200 300) (200 200))
   rect(l9 (-250 3250) (300 1400))
   rect(l9 (-300 -4600) (300 3200))
   rect(l9 (-300 -2900) (450 400))
   rect(l9 (-450 -1550) (300 850))
   text(l10 OUT (-50 500))
   rect(l2 (-350 2650) (450 1500))
   rect(l6 (-450 -5500) (450 900))
  )
  net(5 name(NWELL)
   rect(l3 (0 2950) (2000 3200))
  )
  net(6 name(SUBSTRATE))

  # Devices and their connections
  device(1 D$PMOS
   location(1025 4950)
   param(L 0.25)
   param(W 1.5)
   param(AS 0.675)
   param(AD 0.675)
   param(PS 3.9)
   param(PD 3.9)
   terminal(S 3)
   terminal(G 1)
   terminal(D 4)
   terminal(B 5)
  )
  device(2 D$NMOS
   location(1025 650)
   param(L 0.25)
   param(W 0.9)
   param(AS 0.405)
   param(AD 0.405)
   param(PS 2.7)
   param(PD 2.7)
   terminal(S 2)
   terminal(G 1)
   terminal(D 4)
   terminal(B 6)
  )

 )
)

# Reference netlist
reference(

 # Device class section
 class(PMOS MOS4)
 class(NMOS MOS4)

 # Circuit section
 # Circuits are the hierarchical building blocks of the netlist.
 circuit(INVERTER

  # Nets
  net(1 name(VSS))
  net(2 name(IN))
  net(3 name(OUT))
  net(4 name(NWELL))
  net(5 name(SUBSTRATE))
  net(6 name(VDD))

  # Outgoing pins and their connections to nets
  pin(1 name(VSS))
  pin(2 name(IN))
  pin(3 name(OUT))
  pin(4 name(NWELL))
  pin(5 name(SUBSTRATE))
  pin(6 name(VDD))

  # Devices and their connections
  device(1 PMOS
   name(P)
   param(L 0.25)
   param(W 1.5)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 3)
   terminal(G 2)
   terminal(D 6)
   terminal(B 4)
  )
  device(2 NMOS
   name(N)
   param(L 0.25)
   param(W 0.9)
   param(AS 0)
   param(AD 0)
   param(PS 0)
   param(PD 0)
   terminal(S 1)
   terminal(G 2)
   terminal(D 3)
   terminal(B 5)
  )

 )
)

# Cross reference
xref(
 circuit(INVERTER INVERTER match
  xref(
   net(1 2 match)
   net(5 4 match)
   net(4 3 match)
   net(6 5 match)
   net(3 6 match)
   net(2 1 match)
   pin(() 1 match)
   pin(() 3 match)
   pin(() 2 match)
   pin(() 4 match)
   pin(() 5 match)
   pin(() 0 match)
   device(2 2 match)
   device(1 1 match)
  )
 )
)