mirror of https://github.com/KLayout/klayout.git
33 lines
1.1 KiB
Groff
33 lines
1.1 KiB
Groff
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* Extracted by KLayout
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.INCLUDE 'models.cir'
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.SUBCKT RINGO FB VDD OUT ENABLE VSS
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X$1 VDD \$1 VSS VDD FB ENABLE VSS ND2X1
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X$2 VDD \$2 VSS VDD \$1 VSS INVX1
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X$3 VDD \$3 VSS VDD \$2 VSS INVX1
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X$4 VDD \$4 VSS VDD \$3 VSS INVX1
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X$5 VDD \$5 VSS VDD \$4 VSS INVX1
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X$6 VDD \$6 VSS VDD \$5 VSS INVX1
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X$7 VDD \$7 VSS VDD \$6 VSS INVX1
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X$8 VDD \$8 VSS VDD \$7 VSS INVX1
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X$9 VDD \$9 VSS VDD \$8 VSS INVX1
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X$10 VDD \$10 VSS VDD \$9 VSS INVX1
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X$11 VDD FB VSS VDD \$10 VSS INVX1
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X$12 VDD OUT VSS VDD FB VSS INVX1
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.ENDS RINGO
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.SUBCKT INVX1 VDD OUT VSS \$4 IN SUBSTRATE
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X$1 VDD IN OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.6375 PS=3.85 PD=3.85
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X$2 VSS IN OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.40375
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+ PS=2.75 PD=2.75
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.ENDS INVX1
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.SUBCKT ND2X1 VDD OUT VSS \$4 B A SUBSTRATE
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X$1 OUT A VDD \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.6375 AD=0.3375 PS=3.85 PD=1.95
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X$2 VDD B OUT \$4 PMOS PARAMS: L=0.25 W=1.5 AS=0.3375 AD=0.6375 PS=1.95 PD=3.85
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X$3 VSS A \$I3 SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.40375 AD=0.21375
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+ PS=2.75 PD=1.4
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X$4 \$I3 B OUT SUBSTRATE NMOS PARAMS: L=0.25 W=0.95 AS=0.21375 AD=0.40375
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+ PS=1.4 PD=2.75
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.ENDS ND2X1
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