2019-07-02 02:03:58 +02:00
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source("inv.oas", "INVERTER")
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deep
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# Reports generated
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# LVS report to inv.lvsdb
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2019-07-12 17:43:43 +02:00
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report_lvs("inv.lvsdb", true)
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2019-07-02 02:03:58 +02:00
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# Write extracted netlist to inv_extracted.cir
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target_netlist("inv_extracted.cir", write_spice, "Extracted by KLayout")
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# Drawing layers
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nwell = input(1, 0)
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active = input(2, 0)
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pplus = input(3, 0)
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nplus = input(4, 0)
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poly = input(5, 0)
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contact = input(6, 0)
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metal1 = input(7, 0)
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metal1_lbl = labels(7, 1)
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via1 = input(8, 0)
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metal2 = input(9, 0)
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metal2_lbl = labels(9, 1)
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# Bulk layer for terminal provisioning
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bulk = polygon_layer
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# Computed layers
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active_in_nwell = active & nwell
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pactive = active_in_nwell & pplus
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pgate = pactive & poly
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psd = pactive - pgate
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active_outside_nwell = active - nwell
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nactive = active_outside_nwell & nplus
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ngate = nactive & poly
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nsd = nactive - ngate
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# Device extraction
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# PMOS transistor device extraction
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extract_devices(mos4("PMOS"), { "SD" => psd, "G" => pgate, "W" => nwell,
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"tS" => psd, "tD" => psd, "tG" => poly, "tW" => nwell })
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# NMOS transistor device extraction
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extract_devices(mos4("NMOS"), { "SD" => nsd, "G" => ngate, "W" => bulk,
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"tS" => nsd, "tD" => nsd, "tG" => poly, "tW" => bulk })
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# Define connectivity for netlist extraction
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# Inter-layer
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connect(psd, contact)
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connect(nsd, contact)
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connect(poly, contact)
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connect(contact, metal1)
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connect(metal1, metal1_lbl) # attaches labels
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connect(metal1, via1)
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connect(via1, metal2)
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connect(metal2, metal2_lbl) # attaches labels
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# Global
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connect_global(bulk, "SUBSTRATE")
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connect_global(nwell, "NWELL")
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# Compare section
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schematic("inv.cir")
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compare
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