Files
iverilog/tgt-vhdl
Nick Gasson e49b796a51 Fix for pr3397689.
This is caused by a bug in some simple pattern matching the VHDL target does to try
and produce more idiomatic code in common cases (e.g. FFs with asynchronous resets in
this case). This patch just restricts the kinds of if-statements we use this
optimisation for.
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