iverilog/vhdlpp
Larry Doolittle be17bfc0e9 Spelling fixes
Mostly comments.
One user-visible string ("Evalutated to ") changed in the debug_eval_tree case.
2014-01-30 15:34:20 -08:00
..
Makefile.in Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
README.txt Spelling fixes to vhdlpp tree 2012-05-17 16:42:03 -07:00
architec.cc Rework scope types and constants so we can tell imported from local names. 2013-06-12 14:09:07 -07:00
architec.h Rework scope types and constants so we can tell imported from local names. 2013-06-12 14:09:07 -07:00
architec_debug.cc updated FSF-address 2012-08-29 10:12:10 -07:00
architec_elaborate.cc Handle rising_edge and falling_edge functions. 2013-06-12 14:21:35 -07:00
architec_emit.cc Fix for br942 - allow function declaration in VHDL architecture. 2013-12-11 23:00:58 +00:00
compiler.cc updated FSF-address 2012-08-29 10:12:10 -07:00
compiler.h Basic structure for emitting packages. 2013-06-12 14:09:07 -07:00
debug.cc Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
entity.cc updated FSF-address 2012-08-29 10:12:10 -07:00
entity.h updated FSF-address 2012-08-29 10:12:10 -07:00
entity_elaborate.cc Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
entity_emit.cc updated FSF-address 2012-08-29 10:12:10 -07:00
entity_stream.cc updated FSF-address 2012-08-29 10:12:10 -07:00
expression.cc Do a better job of figuring the vtype of an expression. 2013-06-12 14:21:36 -07:00
expression.h Do a better job of figuring the vtype of an expression. 2013-06-12 14:21:36 -07:00
expression_debug.cc updated FSF-address 2012-08-29 10:12:10 -07:00
expression_elaborate.cc Fix more compile warnings and a minor bug 2013-07-11 19:10:25 -07:00
expression_emit.cc Spelling fixes 2014-01-30 15:34:20 -08:00
expression_evaluate.cc Remove some compile warnings 2013-04-17 17:13:22 -07:00
expression_stream.cc Improve error handling. 2012-11-02 19:30:12 -07:00
ivl_assert.h updated FSF-address 2012-08-29 10:12:10 -07:00
lexor.lex updated FSF-address 2012-08-29 10:12:10 -07:00
lexor_keyword.gperf properly handle vhdl open ports in component instantiations. 2011-06-12 16:59:07 -07:00
library.cc Remove a compile warning 2013-07-11 18:03:00 -07:00
main.cc Basic structure for emitting packages. 2013-06-12 14:09:07 -07:00
package.cc Parse (to sorry messages) unbounded array definitions. 2013-06-12 14:21:36 -07:00
package.h Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
package_emit.cc Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
parse.y Fix for br942 - allow function declaration in VHDL architecture. 2013-12-11 23:00:58 +00:00
parse_api.h updated FSF-address 2012-08-29 10:12:10 -07:00
parse_misc.cc Parse (to sorry messages) unbounded array definitions. 2013-06-12 14:21:36 -07:00
parse_misc.h Parse (to sorry messages) unbounded array definitions. 2013-06-12 14:21:36 -07:00
parse_types.h Better simple_expression parse rules. 2013-06-12 14:21:36 -07:00
parse_wrap.h Function declarations in packages 2013-06-12 14:09:07 -07:00
scope.cc Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
scope.h Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
sequential.cc Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
sequential.h Fix SV emit of ForLoopStatement and ReturnStmt. 2013-06-12 14:09:07 -07:00
sequential_debug.cc Parse VHDL subprogram bodies and return statements. 2012-11-03 09:54:07 -07:00
sequential_elaborate.cc updated FSF-address 2012-08-29 10:12:10 -07:00
sequential_emit.cc Fix SV emit of ForLoopStatement and ReturnStmt. 2013-06-12 14:09:07 -07:00
subprogram.cc Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
subprogram.h Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
subprogram_emit.cc SV emit function ports in package subprograms. 2013-06-12 14:09:07 -07:00
vhdlint.cc updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlint.h updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlnum.h Introductory changes for numbers handling 2011-02-10 18:34:13 -08:00
vhdlpp_config.h.in updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlreal.cc updated FSF-address 2012-08-29 10:12:10 -07:00
vhdlreal.h updated FSF-address 2012-08-29 10:12:10 -07:00
vsignal.cc updated FSF-address 2012-08-29 10:12:10 -07:00
vsignal.h updated FSF-address 2012-08-29 10:12:10 -07:00
vtype.cc Fix dump of primitive CHARACTER types. 2013-06-12 14:09:07 -07:00
vtype.h Do a better job of figuring the vtype of an expression. 2013-06-12 14:21:36 -07:00
vtype_elaborate.cc Elaborate VHDL entity port types/expressions. 2013-06-12 14:21:35 -07:00
vtype_emit.cc Basic structure for emitting packages. 2013-06-12 14:09:07 -07:00
vtype_match.cc Implement subprogram bodies in package bodies. 2013-06-12 14:09:07 -07:00
vtype_stream.cc Some shorthand type marks in write_to_stream. 2013-06-12 14:21:35 -07:00

README.txt

vhdlpp COMMAND LINE FLAGS:

-D <token>
  Debug flags. The token can be:

  * yydebug | no-yydebug

  * entities=<path>

-L <path>
  Library path. Add the directory name to the front of the library
  search path. The library search path is initially empty.

-V
  Display version on stdout

-v
  Verbose: Display version on stderr, and enable verbose messages to
  stderr.

-w <path>
  Work path. This is the directory where the working directory is.


LIBRARY FORMAT:

The vhdlpp program stores libraries as directory that contain
packages. The name of the directory (in lower case) is the name of the
library as used on the "import" statement. Within that library, there
are packages in files named <foo>.pkg. For example:

    <directory>/...
       sample/...
         test1.pkg
	 test2.pkg
       bar/...
         test3.pkg

Use the "+vhdl-libdir+<directory>" record in a config file to tell
Icarus Verilog that <directory> is a place to look for libraries. Then
in your VHDL code, access packages like this:

    library sample;
    library bar;
    use sample.test1.all;
    use bar.test3.all;

The *.pkg files are just VHDL code containing only the package with
the same name. When Icarus Verilog encounters the "use <lib>.<name>.*;"
statement, it looks for the <name>.pkg file in the <lib> library and
parses that file to get the package header declared therein.