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iverilog/ivtest/ivltests/sv_interface_identifier_instance_name.v
T
Lars-Peter Clausen 3c3f46099d Add regression tests for interface identifier names
Check separately that a visible interface name can be reused as a member,
modport, interface port, ordinary port, interface instance and procedural block
name.

Also check an attributed forward interface port type after another ANSI port
declaration.

Signed-off-by: Lars-Peter Clausen <[email protected]>
2026-07-18 11:22:09 -07:00

24 lines
306 B
Verilog

// Check that an interface instance can match its interface type name.
interface I;
logic value;
endinterface
module test;
I I();
initial begin
I.value = 1'b1;
#1;
if (I.value !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule