Add regression tests for interface identifier names
Check separately that a visible interface name can be reused as a member, modport, interface port, ordinary port, interface instance and procedural block name. Also check an attributed forward interface port type after another ANSI port declaration. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
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// Check that a procedural block can match a visible interface name.
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interface I;
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endinterface
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module test;
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initial begin : I
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$display("PASSED");
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end
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endmodule
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@ -0,0 +1,23 @@
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// Check that an interface instance can match its interface type name.
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interface I;
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logic value;
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endinterface
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module test;
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I I();
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initial begin
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I.value = 1'b1;
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#1;
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if (I.value !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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@ -0,0 +1,30 @@
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// Check that an interface port can match its interface type name.
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interface I;
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logic value;
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endinterface
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module dut(I I);
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assign I.value = 1'b1;
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endmodule
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module test;
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I bus();
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dut i_dut(bus);
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initial begin
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#1;
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if (bus.value !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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@ -0,0 +1,23 @@
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// Check that an interface member can match the interface name.
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interface I;
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logic I;
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endinterface
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module test;
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I bus();
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initial begin
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bus.I = 1'b1;
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#1;
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if (bus.I !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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@ -0,0 +1,31 @@
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// Check that a modport can match the interface name.
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interface I;
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logic value;
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modport I(output value);
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endinterface
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module dut(I.I bus);
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assign bus.value = 1'b1;
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endmodule
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module test;
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I bus();
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dut i_dut(bus);
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initial begin
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#1;
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if (bus.value !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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@ -0,0 +1,32 @@
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// Check that an ordinary port can match a visible interface name.
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interface I;
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endinterface
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module dut(
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input wire I,
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output wire value
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);
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assign value = I;
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endmodule
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module test;
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wire value;
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dut i_dut(.I(1'b1), .value(value));
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initial begin
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#1;
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if (value !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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@ -0,0 +1,41 @@
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// Check that an attribute does not prevent recognizing a forward interface
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// port type after another ANSI port declaration.
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module dut(
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input wire enable,
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(* keep = 1 *) bus_if.producer bus,
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bus_if mirror
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);
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assign bus.value = enable;
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assign mirror.value = bus.value;
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endmodule
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interface bus_if;
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logic value;
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modport producer(output value);
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endinterface
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module test;
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reg enable;
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bus_if bus();
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bus_if mirror();
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dut i_dut(enable, bus, mirror);
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initial begin
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enable = 1'b1;
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#1;
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if (bus.value !== 1'b1 || mirror.value !== 1'b1) begin
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$display("FAILED");
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$finish;
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end
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$display("PASSED");
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end
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endmodule
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@ -315,7 +315,14 @@ sv_default_port_value3 vvp_tests/sv_default_port_value3.json
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sv_foreach9 vvp_tests/sv_foreach9.json
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sv_foreach10 vvp_tests/sv_foreach10.json
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sv_interface vvp_tests/sv_interface.json
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sv_interface_identifier_block_name vvp_tests/sv_interface_identifier_block_name.json
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sv_interface_identifier_instance_name vvp_tests/sv_interface_identifier_instance_name.json
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sv_interface_identifier_interface_port_name vvp_tests/sv_interface_identifier_interface_port_name.json
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sv_interface_identifier_member_name vvp_tests/sv_interface_identifier_member_name.json
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sv_interface_identifier_modport_name vvp_tests/sv_interface_identifier_modport_name.json
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sv_interface_identifier_port_name vvp_tests/sv_interface_identifier_port_name.json
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sv_interface_port_basic vvp_tests/sv_interface_port_basic.json
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sv_interface_port_forward_type_after_port vvp_tests/sv_interface_port_forward_type_after_port.json
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sv_interface_port_missing_type_fail vvp_tests/sv_interface_port_missing_type_fail.json
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sv_interface_port_missing_modport_fail vvp_tests/sv_interface_port_missing_modport_fail.json
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sv_interface_port_non_interface_actual_fail vvp_tests/sv_interface_port_non_interface_actual_fail.json
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{
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"type" : "normal",
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"source" : "sv_interface_identifier_block_name.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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{
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"type" : "normal",
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"source" : "sv_interface_identifier_instance_name.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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{
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"type" : "normal",
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"source" : "sv_interface_identifier_interface_port_name.v",
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"iverilog-args" : [ "-g2005-sv" ],
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"vlog95" : {
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"__comment" : "vlog95 redeclares connected interface instances as nets",
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"type" : "TE"
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}
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}
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{
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"type" : "normal",
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"source" : "sv_interface_identifier_member_name.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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{
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"type" : "normal",
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"source" : "sv_interface_identifier_modport_name.v",
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"iverilog-args" : [ "-g2005-sv" ],
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"vlog95" : {
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"__comment" : "vlog95 redeclares connected interface instances as nets",
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"type" : "TE"
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}
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}
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{
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"type" : "normal",
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"source" : "sv_interface_identifier_port_name.v",
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"iverilog-args" : [ "-g2005-sv" ]
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}
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{
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"type" : "normal",
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"source" : "sv_interface_port_forward_type_after_port.v",
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"iverilog-args" : [ "-g2005-sv" ],
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"vlog95" : {
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"__comment" : "vlog95 redeclares connected interface instances as nets",
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"type" : "TE"
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}
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}
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