Add regression tests for interface identifier names

Check separately that a visible interface name can be reused as a member,
modport, interface port, ordinary port, interface instance and procedural block
name.

Also check an attributed forward interface port type after another ANSI port
declaration.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
This commit is contained in:
Lars-Peter Clausen 2026-07-12 12:13:25 -07:00
parent 60f366790b
commit 3c3f46099d
15 changed files with 246 additions and 0 deletions

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@ -0,0 +1,12 @@
// Check that a procedural block can match a visible interface name.
interface I;
endinterface
module test;
initial begin : I
$display("PASSED");
end
endmodule

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@ -0,0 +1,23 @@
// Check that an interface instance can match its interface type name.
interface I;
logic value;
endinterface
module test;
I I();
initial begin
I.value = 1'b1;
#1;
if (I.value !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule

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@ -0,0 +1,30 @@
// Check that an interface port can match its interface type name.
interface I;
logic value;
endinterface
module dut(I I);
assign I.value = 1'b1;
endmodule
module test;
I bus();
dut i_dut(bus);
initial begin
#1;
if (bus.value !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule

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@ -0,0 +1,23 @@
// Check that an interface member can match the interface name.
interface I;
logic I;
endinterface
module test;
I bus();
initial begin
bus.I = 1'b1;
#1;
if (bus.I !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule

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@ -0,0 +1,31 @@
// Check that a modport can match the interface name.
interface I;
logic value;
modport I(output value);
endinterface
module dut(I.I bus);
assign bus.value = 1'b1;
endmodule
module test;
I bus();
dut i_dut(bus);
initial begin
#1;
if (bus.value !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule

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@ -0,0 +1,32 @@
// Check that an ordinary port can match a visible interface name.
interface I;
endinterface
module dut(
input wire I,
output wire value
);
assign value = I;
endmodule
module test;
wire value;
dut i_dut(.I(1'b1), .value(value));
initial begin
#1;
if (value !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule

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@ -0,0 +1,41 @@
// Check that an attribute does not prevent recognizing a forward interface
// port type after another ANSI port declaration.
module dut(
input wire enable,
(* keep = 1 *) bus_if.producer bus,
bus_if mirror
);
assign bus.value = enable;
assign mirror.value = bus.value;
endmodule
interface bus_if;
logic value;
modport producer(output value);
endinterface
module test;
reg enable;
bus_if bus();
bus_if mirror();
dut i_dut(enable, bus, mirror);
initial begin
enable = 1'b1;
#1;
if (bus.value !== 1'b1 || mirror.value !== 1'b1) begin
$display("FAILED");
$finish;
end
$display("PASSED");
end
endmodule

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@ -315,7 +315,14 @@ sv_default_port_value3 vvp_tests/sv_default_port_value3.json
sv_foreach9 vvp_tests/sv_foreach9.json
sv_foreach10 vvp_tests/sv_foreach10.json
sv_interface vvp_tests/sv_interface.json
sv_interface_identifier_block_name vvp_tests/sv_interface_identifier_block_name.json
sv_interface_identifier_instance_name vvp_tests/sv_interface_identifier_instance_name.json
sv_interface_identifier_interface_port_name vvp_tests/sv_interface_identifier_interface_port_name.json
sv_interface_identifier_member_name vvp_tests/sv_interface_identifier_member_name.json
sv_interface_identifier_modport_name vvp_tests/sv_interface_identifier_modport_name.json
sv_interface_identifier_port_name vvp_tests/sv_interface_identifier_port_name.json
sv_interface_port_basic vvp_tests/sv_interface_port_basic.json
sv_interface_port_forward_type_after_port vvp_tests/sv_interface_port_forward_type_after_port.json
sv_interface_port_missing_type_fail vvp_tests/sv_interface_port_missing_type_fail.json
sv_interface_port_missing_modport_fail vvp_tests/sv_interface_port_missing_modport_fail.json
sv_interface_port_non_interface_actual_fail vvp_tests/sv_interface_port_non_interface_actual_fail.json

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@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_interface_identifier_block_name.v",
"iverilog-args" : [ "-g2005-sv" ]
}

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@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_interface_identifier_instance_name.v",
"iverilog-args" : [ "-g2005-sv" ]
}

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@ -0,0 +1,9 @@
{
"type" : "normal",
"source" : "sv_interface_identifier_interface_port_name.v",
"iverilog-args" : [ "-g2005-sv" ],
"vlog95" : {
"__comment" : "vlog95 redeclares connected interface instances as nets",
"type" : "TE"
}
}

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@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_interface_identifier_member_name.v",
"iverilog-args" : [ "-g2005-sv" ]
}

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@ -0,0 +1,9 @@
{
"type" : "normal",
"source" : "sv_interface_identifier_modport_name.v",
"iverilog-args" : [ "-g2005-sv" ],
"vlog95" : {
"__comment" : "vlog95 redeclares connected interface instances as nets",
"type" : "TE"
}
}

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@ -0,0 +1,5 @@
{
"type" : "normal",
"source" : "sv_interface_identifier_port_name.v",
"iverilog-args" : [ "-g2005-sv" ]
}

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@ -0,0 +1,9 @@
{
"type" : "normal",
"source" : "sv_interface_port_forward_type_after_port.v",
"iverilog-args" : [ "-g2005-sv" ],
"vlog95" : {
"__comment" : "vlog95 redeclares connected interface instances as nets",
"type" : "TE"
}
}