iverilog/Documentation/usage
William P. Moore f402e2142d vpi: add native structural-connectivity object model
Implement the IEEE 1364 structural VPI objects that Icarus previously left
unimplemented, so a single-source consumer (e.g. a dataflow/waveform viewer)
gets real data instead of empty fallbacks. Each object is sourced faithfully
from the compiler and threaded ivl -> tgt-vvp -> .vvp directive -> assembler
-> runtime __vpi* -> scope iterator -> vpi_user.h constants.

* vpiProcess (always/initial/final): .process directive from ivl_design_process;
  object reports vpiType/vpiLineNo/vpiFile/vpiScope.

* vpiPrimitive / vpiPrimTerm (gate/switch/UDP): .primitive directive from
  ivl_scope_logs; reports vpiPrimType, vpiSize (#inputs), name, location, and
  iterates terminals (vpiDirection, vpiTermIndex).

* vpiDriver: the tri resolver already retains each driver's value+strength;
  tgt-vvp tags each input with its driver scope (.resolv_drv), and
  vpi_iterate(vpiDriver, net) exposes per-driver value (vpiStrengthVal) and
  scope. signal->node->fun is the resolver, so no extra linkage is needed.

* vpiContAssign (+vpiLhs/vpiRhs): continuous assignments are preserved through
  the frontend (NetScope records each lval/rval/location/drive in
  PGAssign::elaborate; dll_target::end_design builds ivl_cont_assign_s, exposed
  via the new ivl_scope_cassigns/ivl_cassign_* API); tgt-vvp emits .contassign
  and the runtime materialises __vpiContAssign. vpiLhs/size/location are always
  faithful; vpiRhs resolves to the r-value net for simple assigns and is null
  for an expression r-value (anonymous synthesised temp).

* EVCD ($dumpports) inout conflict states: sys_evcd.c walks vpiDriver on an
  inout's net, separates module-side from external drives by scope, and maps
  the pair to the full IEEE 1364-2005 18.4.3 state characters (0/1/?/F, the
  A/a/B/b/C/c conflicts, and d/u/l/h by drive strength) instead of collapsing
  a genuine bus conflict to '?'. New ivtest evcd_inout covers it.

Full Verilog regression (regress-vlg.list) stays clean: the only failures are
pre-existing (gold-less Expected-Fail tests, a VHDL test, a test needing
-gno-io-range-error, and a pre-existing .port_info bug).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-06-19 18:53:47 -06:00
..
GTKWave_Example2.png Document using gtkwave with Icarus Verilog 2022-04-18 20:01:59 -07:00
command_files.rst Spelling and space cleanup 2023-05-31 22:44:13 -07:00
command_line_flags.rst Add 2017 and 2023 language flag support 2026-05-16 15:40:37 -07:00
getting_started.rst Spelling and space cleanup 2023-05-31 22:44:13 -07:00
icarus_verilog_extensions.rst Move details of non-standard behaviour from README to Documentation. 2025-08-03 18:19:45 +01:00
icarus_verilog_quirks.rst Move details of non-standard behaviour from README to Documentation. 2025-08-03 18:19:45 +01:00
index.rst Fix issues with waveform viewer documentation and mention Surfer 2025-07-06 12:47:35 +02:00
installation.rst Update documentation to clarify that 'version.exe' is no longer used 2026-04-30 09:11:21 +02:00
ivlpp_flags.rst Move textfiles to documentation 2023-06-09 13:30:44 +02:00
reporting_issues.rst Fix typo: contributer -> contributor 2026-03-05 22:48:57 +01:00
simulation.rst Spelling and space cleanup 2023-05-31 22:44:13 -07:00
verilog_attributes.rst Spelling and space cleanup 2023-05-31 22:44:13 -07:00
vhdlpp_flags.rst Move textfiles to documentation 2023-06-09 13:30:44 +02:00
vpi.rst Update VPI example to not have warnings 2025-02-13 01:04:41 -08:00
vvp_debug.rst Move textfiles to documentation 2023-06-09 13:30:44 +02:00
vvp_flags.rst Fix issues with waveform viewer documentation and mention Surfer 2025-07-06 12:47:35 +02:00
vvp_library.rst Configure with --enable-libvvp builds a shared library containing 2024-01-24 11:46:02 +00:00
waveform_viewer.rst vpi: add native structural-connectivity object model 2026-06-19 18:53:47 -06:00