iverilog

History

steve 00cacae2a3 Generate constant symbols for supply nets.		2001-07-28 03:18:50 +00:00
..
.cvsignore	Add the tgt-vvp code generator target.	2001-03-19 01:20:46 +00:00
Makefile.in	make distclean target.	2001-05-20 17:13:27 +00:00
README.txt	Add a README for notes about the vvp target.	2001-03-25 18:10:39 +00:00
configure.in	Mingw32 support (Venkat Iyer)	2001-05-20 15:09:39 +00:00
eval_expr.c	Handle part select expressions as variants of	2001-07-27 04:51:44 +00:00
vvp.c	Make vvp output executable (Stephan Boettcher)	2001-07-16 18:26:08 +00:00
vvp_priv.h	1. Logic with more than 4 inputs	2001-06-18 03:10:34 +00:00
vvp_process.c	Evaluate part selects when passed to system tasks.	2001-07-28 01:18:07 +00:00
vvp_scope.c	Generate constant symbols for supply nets.	2001-07-28 03:18:50 +00:00

README.txt

THE VVP TARGET

SYMBOL NAME CONVENTIONS

There are some naming conventions that the vp target uses for
generating symbol names.

* wires and regs

Nets and variables are named V_<full-name> where <full-name> is the
full hierarchical name of the signal.

* Logic devices

Logic devices (and, or, buf, bufz, etc.) are named L_<full_name>. In
this case the symbol is attached to a functor that is the output of
the logic device.